38 lines
838 B
Coq
38 lines
838 B
Coq
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// See LICENSE.SiFive for license details.
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/** This black-boxes a Clock Divider by 3.
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* The output clock is phase-aligned to the input clock.
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* Do NOT use this in synthesis; the duty cycle is 2:1.
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*
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* Because Chisel does not support
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* blocking assignments, it is impossible
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* to create a deterministic divided clock.
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*
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* @param clk_out Divided Clock
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* @param clk_in Clock Input
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*
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*/
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module ClockDivider3 (output reg clk_out, input clk_in);
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reg delay;
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initial begin
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clk_out = 1'b0;
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delay = 1'b0;
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end
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always @(posedge clk_in) begin
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if (clk_out == 1'b0) begin
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clk_out = 1'b1;
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delay <= 1'b0;
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end else if (delay == 1'b1) begin
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clk_out = 1'b0;
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delay <= 1'b0;
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end else begin
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delay <= 1'b1;
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end
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end
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endmodule // ClockDivider3
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