86 lines
2.7 KiB
Scala
86 lines
2.7 KiB
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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/** Collects interrupts from internal and external devices and feeds them into the PLIC */
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class InterruptBusWrapper(implicit p: Parameters) {
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val int_bus = LazyModule(new IntXbar) // Interrupt crossbar
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private def synchronize(sync: Int): IntInwardNode = {
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val asyncXing = LazyModule(new IntXing(sync))
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int_bus.intnode := asyncXing.intnode
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asyncXing.intnode
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}
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def fromAsync: IntInwardNode = synchronize(3)
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def fromRational: IntInwardNode = synchronize(1)
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def fromSync: IntInwardNode = int_bus.intnode
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def toPLIC: IntOutwardNode = int_bus.intnode
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}
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trait HasInterruptBus {
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implicit val p: Parameters
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val ibus = new InterruptBusWrapper
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}
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/** Specifies the number of external interrupts */
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case object NExtTopInterrupts extends Field[Int]
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/** This trait adds externally driven interrupts to the system.
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* However, it should not be used directly; instead one of the below
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* synchronization wiring child traits should be used.
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*/
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abstract trait HasExtInterrupts extends HasInterruptBus {
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private val device = new Device with DeviceInterrupts {
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def describe(resources: ResourceBindings): Description = {
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Description("soc/external-interrupts", describeInterrupts(resources))
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}
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}
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val nExtInterrupts = p(NExtTopInterrupts)
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val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
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}
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/** This trait should be used if the External Interrupts have NOT
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* already been synchronized to the Periphery (PLIC) Clock.
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*/
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trait HasAsyncExtInterrupts extends HasExtInterrupts {
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if (nExtInterrupts > 0) {
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ibus.fromAsync := extInterrupts
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}
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}
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/** This trait can be used if the External Interrupts have already been synchronized
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* to the Periphery (PLIC) Clock.
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*/
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trait HasSyncExtInterrupts extends HasExtInterrupts {
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if (nExtInterrupts > 0) {
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ibus.fromSync := extInterrupts
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}
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}
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasExtInterruptsBundle {
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val interrupts: UInt
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def tieOffInterrupts(dummy: Int = 1) {
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interrupts := UInt(0)
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}
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}
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/** This trait performs the translation from a UInt IO into Diplomatic Interrupts.
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* The wiring must be done in the concrete LazyModuleImp.
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*/
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trait HasExtInterruptsModuleImp extends LazyMultiIOModuleImp with HasExtInterruptsBundle {
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val outer: HasExtInterrupts
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val interrupts = IO(UInt(INPUT, width = outer.nExtInterrupts))
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outer.extInterrupts.bundleIn.flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
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}
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