50 lines
1.8 KiB
Scala
50 lines
1.8 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
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class TLHintHandler(passthrough: Boolean = true) extends TLSimpleFactory
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{
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => c.copy(clients = c.clients .map(_.copy(supportsHint = true))) },
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managerFn = { case Seq(m) => m.copy(managers = m.managers.map(_.copy(supportsHint = true))) })
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lazy val module = Module(new TLModule(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val in = io.in(0)
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val out = io.out(0)
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val edgeIn = node.edgesIn(0)
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val edgeOut = node.edgesOut(0)
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(in.a.bits.address) else Bool(true)
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val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
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// Prioritize existing D traffic over HintAck
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in.d.valid := out.d.valid || (bypassD && in.a.valid)
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out.d.ready := in.d.ready
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in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits.source, in.a.bits.size))
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in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready)
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out.a.valid := in.a.valid && !bypassD
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out.a.bits := in.a.bits
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val handleB = if (passthrough) !edgeIn.client.supportsHint(out.b.bits.source) else Bool(true)
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val bypassC = handleB && out.b.bits.opcode === TLMessages.Hint
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// Prioritize existing C traffic over HintAck
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out.c.valid := in.c.valid || (bypassC && in.b.valid)
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in.c.ready := out.c.ready
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out.c.bits := Mux(in.c.valid, in.c.bits, edgeOut.HintAck(out.b.bits.address, out.b.bits.size))
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out.b.ready := Mux(bypassC, out.c.ready && !in.c.valid, in.b.ready)
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in.b.valid := out.b.valid && !bypassC
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in.b.bits := out.b.bits
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})
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}
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