riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
9dc0cbdfa4
rocket-chip/vsrc/backup_mem.v

123 lines
3.0 KiB
Coq
Raw Normal View History

add LICENSE
2014-09-12 19:15:04 +02:00
// See LICENSE for license details.
generate consts.vh from chisel source
2014-09-11 02:14:55 +02:00
`define ceilLog2(x) ( \
(x) > 2**30 ? 31 : \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
(x) > 2**29 ? 30 : \
(x) > 2**28 ? 29 : \
(x) > 2**27 ? 28 : \
(x) > 2**26 ? 27 : \
(x) > 2**25 ? 26 : \
(x) > 2**24 ? 25 : \
(x) > 2**23 ? 24 : \
(x) > 2**22 ? 23 : \
(x) > 2**21 ? 22 : \
(x) > 2**20 ? 21 : \
(x) > 2**19 ? 20 : \
(x) > 2**18 ? 19 : \
(x) > 2**17 ? 18 : \
(x) > 2**16 ? 17 : \
(x) > 2**15 ? 16 : \
(x) > 2**14 ? 15 : \
(x) > 2**13 ? 14 : \
(x) > 2**12 ? 13 : \
(x) > 2**11 ? 12 : \
(x) > 2**10 ? 11 : \
(x) > 2**9 ? 10 : \
(x) > 2**8 ? 9 : \
(x) > 2**7 ? 8 : \
(x) > 2**6 ? 7 : \
(x) > 2**5 ? 6 : \
(x) > 2**4 ? 5 : \
(x) > 2**3 ? 4 : \
(x) > 2**2 ? 3 : \
(x) > 2**1 ? 2 : \
(x) > 2**0 ? 1 : 0)
`ifdef MEM_BACKUP_EN
generate consts.vh from chisel source
2014-09-11 02:14:55 +02:00
module BackupMemory
update for rocket-chip release
2014-09-01 05:26:55 +02:00
(
input clk,
input reset,
input mem_req_valid,
output mem_req_ready,
input mem_req_rw,
Resurrect the backup memory port We need this to work for our chip, and it's not been tested in a long time in upstream -- it didn't even used to build since the Nasti conversion. This makes a few changes: * Rather than calling the backup memory port parameters MEM_*, it calls them MIF_* (to match the MIT* paramater objects). A new name was necessary because the Nasti stuff is now dumped as MEM_*, which has similar names but incompatible values. * p(MIFDataBits) was changed back to 128, as otherwise the backup memory port doesn't work (it only send half a TileLink transaction). 64 also causes readmemh to bail out, but changing the elf2hex parameters works around that. * A configuration was added that enabled the backup memory port in the tester. While this is kind of an awkward way to do it, I want to make sure I can start testing this regularly and this makes it easy to integrate.
2016-02-26 10:29:38 +01:00
input [`MIF_ADDR_BITS-1:0] mem_req_addr,
input [`MIF_TAG_BITS-1:0] mem_req_tag,
update for rocket-chip release
2014-09-01 05:26:55 +02:00
input mem_req_data_valid,
output mem_req_data_ready,
Resurrect the backup memory port We need this to work for our chip, and it's not been tested in a long time in upstream -- it didn't even used to build since the Nasti conversion. This makes a few changes: * Rather than calling the backup memory port parameters MEM_*, it calls them MIF_* (to match the MIT* paramater objects). A new name was necessary because the Nasti stuff is now dumped as MEM_*, which has similar names but incompatible values. * p(MIFDataBits) was changed back to 128, as otherwise the backup memory port doesn't work (it only send half a TileLink transaction). 64 also causes readmemh to bail out, but changing the elf2hex parameters works around that. * A configuration was added that enabled the backup memory port in the tester. While this is kind of an awkward way to do it, I want to make sure I can start testing this regularly and this makes it easy to integrate.
2016-02-26 10:29:38 +01:00
input [`MIF_DATA_BITS-1:0] mem_req_data_bits,
update for rocket-chip release
2014-09-01 05:26:55 +02:00
output reg mem_resp_valid,
Resurrect the backup memory port We need this to work for our chip, and it's not been tested in a long time in upstream -- it didn't even used to build since the Nasti conversion. This makes a few changes: * Rather than calling the backup memory port parameters MEM_*, it calls them MIF_* (to match the MIT* paramater objects). A new name was necessary because the Nasti stuff is now dumped as MEM_*, which has similar names but incompatible values. * p(MIFDataBits) was changed back to 128, as otherwise the backup memory port doesn't work (it only send half a TileLink transaction). 64 also causes readmemh to bail out, but changing the elf2hex parameters works around that. * A configuration was added that enabled the backup memory port in the tester. While this is kind of an awkward way to do it, I want to make sure I can start testing this regularly and this makes it easy to integrate.
2016-02-26 10:29:38 +01:00
output reg [`MIF_DATA_BITS-1:0] mem_resp_data,
output reg [`MIF_TAG_BITS-1:0] mem_resp_tag
update for rocket-chip release
2014-09-01 05:26:55 +02:00
);
Change MIF_DATA_BITS back to 64 It turns out the Chisel C++ backend can't emit correct initialization code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm just going to hack up the backup memory port Verilog harness a bit more to make it work. Note that the backup memory port Verilog already couldn't take arbitrary parameters for MIF_*, so it's not like we're losing any flexibility here.
2016-02-27 20:41:28 +01:00
localparam DATA_CYCLES = 8;
update for rocket-chip release
2014-09-01 05:26:55 +02:00
localparam DEPTH = 2*1024*1024;
reg [`ceilLog2(DATA_CYCLES)-1:0] cnt;
Resurrect the backup memory port We need this to work for our chip, and it's not been tested in a long time in upstream -- it didn't even used to build since the Nasti conversion. This makes a few changes: * Rather than calling the backup memory port parameters MEM_*, it calls them MIF_* (to match the MIT* paramater objects). A new name was necessary because the Nasti stuff is now dumped as MEM_*, which has similar names but incompatible values. * p(MIFDataBits) was changed back to 128, as otherwise the backup memory port doesn't work (it only send half a TileLink transaction). 64 also causes readmemh to bail out, but changing the elf2hex parameters works around that. * A configuration was added that enabled the backup memory port in the tester. While this is kind of an awkward way to do it, I want to make sure I can start testing this regularly and this makes it easy to integrate.
2016-02-26 10:29:38 +01:00
reg [`MIF_TAG_BITS-1:0] tag;
update for rocket-chip release
2014-09-01 05:26:55 +02:00
reg state_busy, state_rw;
Resurrect the backup memory port We need this to work for our chip, and it's not been tested in a long time in upstream -- it didn't even used to build since the Nasti conversion. This makes a few changes: * Rather than calling the backup memory port parameters MEM_*, it calls them MIF_* (to match the MIT* paramater objects). A new name was necessary because the Nasti stuff is now dumped as MEM_*, which has similar names but incompatible values. * p(MIFDataBits) was changed back to 128, as otherwise the backup memory port doesn't work (it only send half a TileLink transaction). 64 also causes readmemh to bail out, but changing the elf2hex parameters works around that. * A configuration was added that enabled the backup memory port in the tester. While this is kind of an awkward way to do it, I want to make sure I can start testing this regularly and this makes it easy to integrate.
2016-02-26 10:29:38 +01:00
reg [`MIF_ADDR_BITS-1:0] addr;
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Change MIF_DATA_BITS back to 64 It turns out the Chisel C++ backend can't emit correct initialization code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm just going to hack up the backup memory port Verilog harness a bit more to make it work. Note that the backup memory port Verilog already couldn't take arbitrary parameters for MIF_*, so it's not like we're losing any flexibility here.
2016-02-27 20:41:28 +01:00
reg [127:0] ram [DEPTH-1:0];
update for rocket-chip release
2014-09-01 05:26:55 +02:00
wire [`ceilLog2(DEPTH)-1:0] ram_addr = state_busy ? {addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt}
: {mem_req_addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt};
wire do_read = mem_req_valid && mem_req_ready && !mem_req_rw || state_busy && !state_rw;
wire do_write = mem_req_data_valid && mem_req_data_ready;
initial
begin : zero
integer i;
for (i = 0; i < DEPTH; i = i+1)
ram[i] = 1'b0;
end
always @(posedge clk)
begin
if (reset)
state_busy <= 1'b0;
else if ((do_read || do_write) && cnt == DATA_CYCLES-1)
state_busy <= 1'b0;
else if (mem_req_valid && mem_req_ready)
state_busy <= 1'b1;
if (!state_busy && mem_req_valid)
begin
state_rw <= mem_req_rw;
tag <= mem_req_tag;
addr <= mem_req_addr;
end
if (reset)
cnt <= 1'b0;
else if(do_read || do_write)
cnt <= cnt + 1'b1;
if (do_write)
Change MIF_DATA_BITS back to 64 It turns out the Chisel C++ backend can't emit correct initialization code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm just going to hack up the backup memory port Verilog harness a bit more to make it work. Note that the backup memory port Verilog already couldn't take arbitrary parameters for MIF_*, so it's not like we're losing any flexibility here.
2016-02-27 20:41:28 +01:00
if (ram_addr[0] == 1'b0)
ram[ram_addr/2][63:0] <= mem_req_data_bits;
else
ram[ram_addr/2][127:64] <= mem_req_data_bits;
update for rocket-chip release
2014-09-01 05:26:55 +02:00
else
Change MIF_DATA_BITS back to 64 It turns out the Chisel C++ backend can't emit correct initialization code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm just going to hack up the backup memory port Verilog harness a bit more to make it work. Note that the backup memory port Verilog already couldn't take arbitrary parameters for MIF_*, so it's not like we're losing any flexibility here.
2016-02-27 20:41:28 +01:00
if (ram_addr[0] == 1'b0)
mem_resp_data <= ram[ram_addr/2][63:0];
else
mem_resp_data <= ram[ram_addr/2][127:64];
update for rocket-chip release
2014-09-01 05:26:55 +02:00
if (reset)
mem_resp_valid <= 1'b0;
else
mem_resp_valid <= do_read;
mem_resp_tag <= state_busy ? tag : mem_req_tag;
end
assign mem_req_ready = !state_busy;
assign mem_req_data_ready = state_busy && state_rw;
endmodule
`endif
Copy Permalink