2015-07-28 09:23:31 +02:00
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#--------------------------------------------------------------------
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# Verilog Generation
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#--------------------------------------------------------------------
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$(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d : $(chisel_srcs)
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cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(CHISEL_ARGS) --configDump --noInlineMem"
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cd $(generated_dir) && \
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if [ -a $(MODEL).$(CONFIG).conf ]; then \
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$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \
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fi
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$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
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echo "\`ifndef CONST_VH" > $@
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echo "\`define CONST_VH" >> $@
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sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
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2015-10-31 05:14:33 +01:00
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echo "\`define TBVFRAG \"$(MODEL).$(CONFIG).tb.vfrag\"" >> $@
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2015-07-28 09:23:31 +02:00
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echo "\`endif // CONST_VH" >> $@
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$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
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2015-10-22 03:23:58 +02:00
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cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
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2015-07-28 09:23:31 +02:00
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2014-09-01 05:26:55 +02:00
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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$(sim_dir)/dramsim2_ini:
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ln -s $(base_dir)/emulator/dramsim2_ini $(sim_dir)/dramsim2_ini
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2015-07-13 23:54:26 +02:00
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$(output_dir)/%.run: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv)
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cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) +loadmem=$< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
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2014-09-01 05:26:55 +02:00
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$(output_dir)/%.out: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv)
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cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) +loadmem=$< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vcd: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +dramsim +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) +loadmem=$< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vpd: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +dramsim +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +loadmem=$< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.saif: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv_debug)
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cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +dramsim +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +loadmem=$<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
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2015-09-10 07:37:47 +02:00
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run: run-asm-tests run-bmark-tests
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run-debug: run-asm-tests-debug run-bmark-tests-debug
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2015-07-13 23:54:26 +02:00
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run-fast: run-asm-tests-fast run-bmark-tests-fast
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2014-09-01 05:26:55 +02:00
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2015-07-13 23:54:26 +02:00
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.PHONY: run-asm-tests run-bmark-tests
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.PHONY: run-asm-tests-debug run-bmark-tests-debug
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.PHONY: run run-debug run-fast
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2014-09-01 05:26:55 +02:00
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junk += $(output_dir)
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