112 lines
3.1 KiB
Scala
112 lines
3.1 KiB
Scala
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package groundtest.unittests
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import cde.Parameters
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class NastiDemuxDriver(n: Int)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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val nasti = new NastiIO
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val select = UInt(OUTPUT, log2Up(n))
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}
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val (s_idle :: s_write_addr :: s_write_data :: s_write_resp ::
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s_read_addr :: s_read_resp :: s_done :: Nil) = Enum(Bits(), 7)
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val state = Reg(init = s_idle)
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val select = Reg(init = UInt(0, log2Up(n)))
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when (state === s_idle && io.start) { state := s_write_addr }
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when (io.nasti.aw.fire()) { state := s_write_data }
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when (io.nasti.w.fire()) { state := s_write_resp }
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when (io.nasti.b.fire()) { state := s_read_addr }
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when (io.nasti.ar.fire()) { state := s_read_resp }
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when (io.nasti.r.fire()) {
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when (select === UInt(n - 1)) {
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state := s_done
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} .otherwise {
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select := select + UInt(1)
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state := s_write_addr
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}
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}
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io.nasti.aw.valid := (state === s_write_addr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b011"))
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io.nasti.w.valid := (state === s_write_data)
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io.nasti.w.bits := NastiWriteDataChannel(data = select)
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io.nasti.b.ready := (state === s_write_resp)
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io.nasti.ar.valid := (state === s_read_addr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt("b011"))
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io.nasti.r.ready := (state === s_read_resp)
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io.finished := (state === s_done)
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io.select := select
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assert(!io.nasti.r.valid || io.nasti.r.bits.data === select,
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"NASTI DeMux test: Read data did not match")
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}
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class NastiDemuxSlave(implicit p: Parameters) extends NastiModule()(p) {
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val io = (new NastiIO).flip
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val (s_write_wait :: s_write_data :: s_write_resp ::
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s_read_wait :: s_read_resp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_write_wait)
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val value = Reg(UInt(width = 64))
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val id = Reg(UInt(width = nastiXIdBits))
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when (io.aw.fire()) {
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id := io.aw.bits.id
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state := s_write_data
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}
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when (io.w.fire()) {
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value := io.w.bits.data
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state := s_write_resp
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}
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when (io.b.fire()) { state := s_read_wait }
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when (io.ar.fire()) {
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id := io.ar.bits.id
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state := s_read_resp
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}
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when (io.r.fire()) { state := s_done }
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io.aw.ready := (state === s_write_wait)
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io.w.ready := (state === s_write_data)
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io.b.valid := (state === s_write_resp)
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io.b.bits := NastiWriteResponseChannel(id = id)
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io.ar.ready := (state === s_read_wait)
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io.r.valid := (state === s_read_resp)
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io.r.bits := NastiReadDataChannel(id = id, data = value)
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}
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class NastiMemoryDemuxTest(implicit p: Parameters) extends UnitTest {
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val nSlaves = 4
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val driver = Module(new NastiDemuxDriver(nSlaves))
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driver.io.start := io.start
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io.finished := driver.io.finished
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val demux = Module(new NastiMemoryDemux(nSlaves))
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demux.io.master <> driver.io.nasti
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demux.io.select := driver.io.select
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for (i <- 0 until nSlaves) {
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val slave = Module(new NastiDemuxSlave)
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slave.io <> demux.io.slaves(i)
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}
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}
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