26 lines
1.3 KiB
INI
26 lines
1.3 KiB
INI
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; COPY THIS FILE AND MODIFY IT TO SUIT YOUR NEEDS
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NUM_CHANS=1 ; number of *logically independent* channels (i.e. each with a separate memory controller); should be a power of 2
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JEDEC_DATA_BUS_BITS=64 ; Always 64 for DDRx; if you want multiple *ganged* channels, set this to N*64
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TRANS_QUEUE_DEPTH=32 ; transaction queue, i.e., CPU-level commands such as: READ 0xbeef
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CMD_QUEUE_DEPTH=32 ; command queue, i.e., DRAM-level commands such as: CAS 544, RAS 4
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EPOCH_LENGTH=100000 ; length of an epoch in cycles (granularity of simulation)
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ROW_BUFFER_POLICY=open_page ; close_page or open_page
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ADDRESS_MAPPING_SCHEME=scheme2 ;valid schemes 1-7; For multiple independent channels, use scheme7 since it has the most parallelism
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SCHEDULING_POLICY=rank_then_bank_round_robin ; bank_then_rank_round_robin or rank_then_bank_round_robin
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QUEUING_STRUCTURE=per_rank ;per_rank or per_rank_per_bank
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;for true/false, please use all lowercase
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DEBUG_TRANS_Q=false
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DEBUG_CMD_Q=false
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DEBUG_ADDR_MAP=false
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DEBUG_BUS=false
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DEBUG_BANKSTATE=false
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DEBUG_BANKS=false
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DEBUG_POWER=false
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VIS_FILE_OUTPUT=false
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USE_LOW_POWER=true ; go into low power mode when idle?
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VERIFICATION_OUTPUT=false ; should be false for normal operation
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TOTAL_ROW_ACCESSES=4 ; maximum number of open page requests to send to the same row before forcing a row close (to prevent starvation)
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