38 lines
1.3 KiB
Scala
38 lines
1.3 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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case class RegField(width: Int, read: RegField.ReadFn, write: RegField.WriteFn)
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object RegField
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{
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type ReadFn = Bool => (Bool, UInt)
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type WriteFn = (Bool, UInt) => Bool
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, noR, noW)
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def apply(n: Int, rw: UInt) : RegField = apply(n, regR(rw), regW(rw))
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def apply(n: Int, r: UInt, w: UInt) : RegField = apply(n, regR(r), regW(w))
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def apply(n: Int, r: UInt, w: WriteFn) : RegField = apply(n, regR(r), w)
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def apply(n: Int, r: ReadFn, w: UInt) : RegField = apply(n, r, regW(w))
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def R(n: Int, r: ReadFn) : RegField = apply(n, r, noW)
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def R(n: Int, r: UInt) : RegField = R(n, regR(r))
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def W(n: Int, w: WriteFn) : RegField = apply(n, noR, w)
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def W(n: Int, w: UInt) : RegField = W(n, regW(w))
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private val noR = (en: Bool) => (Bool(true), UInt(0))
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private val noW = (en: Bool, in: UInt) => Bool(true)
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private def regR(reg: UInt) = (en: Bool) => (Bool(true), reg)
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private def regW(reg: UInt) = (en: Bool, in: UInt) =>
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{
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when (en) { reg := in }
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Bool(true)
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}
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}
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trait HasRegMap
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{
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def regmap(mapping: RegField.Map*): Unit
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}
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