98 lines
4.4 KiB
Scala
98 lines
4.4 KiB
Scala
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import diplomacy._
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import uncore.tilelink2._
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case class TLBPermissions(
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homogeneous: Bool, // if false, the below are undefined
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r: Bool, // readable
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w: Bool, // writeable
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x: Bool, // executable
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c: Bool, // cacheable
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a: Bool, // arithmetic ops
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l: Bool) // logical ops
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object TLBPageLookup
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{
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private case class TLBFixedPermissions(
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r: Boolean, // readable
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w: Boolean, // writeable
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x: Boolean, // executable
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c: Boolean, // cacheable
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a: Boolean, // arithmetic ops
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l: Boolean) { // logical ops
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val useful = r || w || x || c || a || l
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}
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// Unmapped memory is considered to be inhomogeneous
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def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt): UInt => TLBPermissions = {
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require (isPow2(xLen) && xLen >= 8)
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require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8)
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require (isPow2(pageSize) && pageSize >= cacheBlockBytes)
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val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
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val allSizes = TransferSizes(1, cacheBlockBytes)
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val amoSizes = TransferSizes(4, xLen/8)
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val permissions = managers.map { m =>
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require (!m.supportsGet || m.supportsGet .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}")
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require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
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require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
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require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
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require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
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require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
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require (m.supportsAcquireT || !m.supportsAcquireB, s"MemoryMap region ${m.name} supports AcquireB (cached read) but not AcquireT (cached write)... and rocket assumes this")
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(m.address, TLBFixedPermissions(
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r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
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w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
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x = m.executable,
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c = m.supportsAcquireB,
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a = m.supportsArithmetic,
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l = m.supportsLogical))
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}
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val grouped: Map[TLBFixedPermissions, Seq[AddressSet]] = permissions
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.filter(_._2.useful) // get rid of no-permission devices
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.groupBy(_._2) // group by permission type
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.mapValues(seq =>
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AddressSet.unify(seq.flatMap(_._1)) // coalesce same-permission regions
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.filter(_.alignment >= pageSize)) // discard any region that's not big enough
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def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
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val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
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val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList)
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// Find the minimal bits needed to distinguish between yes and no
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val decisionMask = AddressDecoder(Seq(yes, no))
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def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct)
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val (yesf, nof) = (simplify(yes), simplify(no))
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if (yesf.size < no.size) {
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(x: UInt) => yesf.map(_.contains(x)).reduce(_ || _)
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} else {
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(x: UInt) => !nof.map(_.contains(x)).reduce(_ || _)
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}
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}
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// Derive simplified property circuits (don't care when !homo)
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val rfn = lowCostProperty(_.r)
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val wfn = lowCostProperty(_.w)
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val xfn = lowCostProperty(_.x)
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val cfn = lowCostProperty(_.c)
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val afn = lowCostProperty(_.a)
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val lfn = lowCostProperty(_.l)
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val homo = AddressSet.unify(grouped.values.flatten.toList)
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(x: UInt) => TLBPermissions(
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homogeneous = homo.map(_.contains(x)).reduce(_ || _),
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r = rfn(x),
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w = wfn(x),
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x = xfn(x),
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c = cfn(x),
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a = afn(x),
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l = lfn(x))
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}
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}
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