36 lines
821 B
Scala
36 lines
821 B
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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import scala.collection.mutable.{HashMap}
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case class ROMConfig(name: String, depth: Int, width: Int)
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class BlackBoxedROM(c: ROMConfig) extends BlackBox {
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val io = new Bundle {
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val clock = Clock(INPUT)
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val address = UInt(INPUT, log2Ceil(c.depth))
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val oe = Bool(INPUT)
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val me = Bool(INPUT)
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val q = UInt(OUTPUT, c.width)
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}
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override def desiredName: String = c.name
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}
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object ROMGenerator {
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private var finalized = false
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private val roms = HashMap[BlackBoxedROM, ROMConfig]()
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def apply(c: ROMConfig): BlackBoxedROM = {
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require(!finalized)
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val m = Module(new BlackBoxedROM(c))
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roms(m) = c
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m
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}
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def lookup(m: BlackBoxedROM): ROMConfig = {
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finalized = true
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roms(m)
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}
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}
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