2016-11-28 01:16:37 +01:00
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// See LICENSE.SiFive for license details.
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2017-07-07 19:48:16 +02:00
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package freechips.rocketchip.util
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2016-09-15 02:38:54 +02:00
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2016-07-13 04:41:10 +02:00
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import Chisel._
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2016-09-15 02:38:54 +02:00
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import chisel3.util.{DecoupledIO, Decoupled, Irrevocable, IrrevocableIO, ReadyValidIO}
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2016-07-13 04:41:10 +02:00
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2016-09-14 00:34:56 +02:00
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class CrossingIO[T <: Data](gen: T) extends Bundle {
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// Enqueue clock domain
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val enq_clock = Clock(INPUT)
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val enq_reset = Bool(INPUT) // synchronously deasserted wrt. enq_clock
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2016-10-07 05:41:21 +02:00
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val enq = Decoupled(gen).flip
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2016-09-14 00:34:56 +02:00
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// Dequeue clock domain
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val deq_clock = Clock(INPUT)
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val deq_reset = Bool(INPUT) // synchronously deasserted wrt. deq_clock
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val deq = Decoupled(gen)
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}
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abstract class Crossing[T <: Data] extends Module {
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val io: CrossingIO[T]
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2016-07-13 04:41:10 +02:00
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}
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