24 lines
754 B
Scala
24 lines
754 B
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.interrupts
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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class IntXbar()(implicit p: Parameters) extends LazyModule
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{
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val intnode = IntNexusNode(
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
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sourceFn = { seq =>
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IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten)
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})
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lazy val module = new LazyModuleImp(this) {
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val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
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intnode.out.foreach { case (o, _) => o := cat }
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}
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}
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