62 lines
1.7 KiB
Scala
62 lines
1.7 KiB
Scala
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// See LICENSE.SiFive for license details.
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package util
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import Chisel._
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/** Implements the same interface as chisel3.util.Queue, but uses a shift
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* register internally. It is less energy efficient whenever the queue
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* has more than one entry populated, but is faster on the dequeue side.
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* It is efficient for usually-empty flow-through queues. */
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class ShiftQueue[T <: Data](gen: T,
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val entries: Int,
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pipe: Boolean = false,
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flow: Boolean = false)
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extends Module {
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val io = IO(new QueueIO(gen, entries) {
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val mask = UInt(OUTPUT, entries)
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})
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private val ram = Mem(entries, gen)
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private val valid = RegInit(UInt(0, entries))
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private val elts = Reg(Vec(entries, gen))
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private val do_enq = Wire(init=io.enq.fire())
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private val do_deq = Wire(init=io.deq.fire())
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when (do_deq) {
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when (!do_enq) { valid := (valid >> 1) }
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for (i <- 1 until entries)
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when (valid(i)) { elts(i-1) := elts(i) }
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}
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when (do_enq && do_deq) {
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for (i <- 0 until entries)
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when (valid(i) && (if (i == entries-1) true.B else !valid(i+1))) { elts(i) := io.enq.bits }
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}
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when (do_enq && !do_deq) {
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valid := (valid << 1) | UInt(1)
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for (i <- 0 until entries)
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when (!valid(i) && (if (i == 0) true.B else valid(i-1))) { elts(i) := io.enq.bits }
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}
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io.enq.ready := !valid(entries-1)
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io.deq.valid := valid(0)
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io.deq.bits := elts.head
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if (flow) {
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when (io.enq.valid) { io.deq.valid := true.B }
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when (!valid(0)) {
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io.deq.bits := io.enq.bits
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do_deq := false.B
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when (io.deq.ready) { do_enq := false.B }
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}
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}
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if (pipe) {
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when (io.deq.ready) { io.enq.ready := true.B }
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}
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io.count := PopCount(valid)
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io.mask := valid
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}
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