riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
75efc7dee7
rocket-chip/.gitmodules

22 lines
679 B
Plaintext
Raw Normal View History

add submodule riscv-tools
2013-05-10 20:53:55 +02:00
[submodule "riscv-tools"]
path = riscv-tools
Instantiate Debug Module (#119)
2016-06-02 19:53:41 +02:00
url = https://github.com/riscv/riscv-tools.git
add berkeley-hardfloat as submodule
2014-09-08 09:18:49 +02:00
[submodule "hardfloat"]
path = hardfloat
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/ucb-bar/berkeley-hardfloat.git
added CDE library as submodule
2015-10-21 01:22:07 +02:00
[submodule "context-dependent-environments"]
path = context-dependent-environments
url = https://github.com/ucb-bar/context-dependent-environments
Add torture as part of the regression Since the latest Spike fix my torture runs are succeeding, so I can now run it as part of the regression flow.
2016-01-31 05:54:41 +01:00
[submodule "torture"]
path = torture
url = https://github.com/ucb-bar/riscv-torture.git
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
[submodule "chisel3"]
path = chisel3
url = https://github.com/ucb-bar/chisel3.git
[submodule "firrtl"]
path = firrtl
url = https://github.com/ucb-bar/firrtl.git
Add JTAG DTM and test support in simulation Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box
2016-08-19 18:46:43 +02:00
[submodule "openocd"]
path = openocd
url = http://github.com/sifive/openocd.git
Copy Permalink