67 lines
1.9 KiB
Scala
67 lines
1.9 KiB
Scala
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import config._
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import tile._
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import util._
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class PMPConfig extends Bundle {
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val p = UInt(width = 2)
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val a = UInt(width = 2)
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val m = Bool()
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val x = Bool()
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val w = Bool()
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val r = Bool()
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}
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class PMP(implicit p: Parameters) extends CoreBundle()(p) {
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val cfg = new PMPConfig
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val addr = UInt(width = paddrBits - lgAlign)
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def enabled(prv: UInt) = cfg.p.orR && (cfg.m || prv <= PRV.S)
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def locked = cfg.p.andR
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def addrLocked(next: PMP) = locked || next.locked && next.cfg.a(1)
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private def lgAlign = 2
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private def mask = (0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt
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def pow2AddressMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
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val m = mask
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def checkOne(a: UInt) = (~(a >> lgAlign) | m) === (~addr | m)
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var res = checkOne(x)
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for (i <- (1 << lgAlign) until (1 << lgMaxSize) by (1 << lgAlign))
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res = res || (lgSize > log2Ceil(i) && checkOne(x | i))
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res
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}
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def hit(prv: UInt, x: UInt, lgSize: UInt, lgMaxSize: Int) = {
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enabled(prv) && pow2AddressMatch(x, lgSize, lgMaxSize)
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}
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}
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class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
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with HasRocketCoreParameters {
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val io = new Bundle {
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val prv = UInt(INPUT, PRV.SZ)
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val pmp = Vec(nPMPs, new PMP).asInput
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val addr = UInt(INPUT, paddrBits)
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val size = UInt(INPUT, log2Ceil(lgMaxSize + 1))
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val xcpt_if = Bool(OUTPUT)
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val xcpt_ld = Bool(OUTPUT)
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val xcpt_st = Bool(OUTPUT)
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}
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def hits = io.pmp.map(_.hit(io.prv, io.addr, io.size, lgMaxSize))
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val default = io.prv > PRV.S
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val (r, w, x, _) = ((default, default, default, 0.U) /: (io.pmp zip hits).reverse) { case ((r, w, x, pri), (pmp, hit)) =>
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MuxT(hit && pmp.cfg.p >= pri, (pmp.cfg.r, pmp.cfg.w, pmp.cfg.x, pmp.cfg.p), (r, w, x, pri))
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}
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io.xcpt_if := !x
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io.xcpt_ld := !r
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io.xcpt_st := !w
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}
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