2011-10-26 08:02:47 +02:00
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package Top
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2012-02-12 02:20:33 +01:00
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2011-10-26 08:02:47 +02:00
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import Chisel._
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import Node._;
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import Constants._;
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class ioCtrlSboard extends Bundle()
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{
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2012-01-18 19:28:48 +01:00
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val clr = Bool(INPUT);
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val clra = UFix(5, INPUT);
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val set = Bool(INPUT);
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val seta = UFix(5, INPUT);
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val raddra = UFix(5, INPUT);
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val raddrb = UFix(5, INPUT);
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val raddrc = UFix(5, INPUT);
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2012-02-08 08:54:25 +01:00
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val raddrd = UFix(5, INPUT);
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2012-01-18 19:28:48 +01:00
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val stalla = Bool(OUTPUT);
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val stallb = Bool(OUTPUT);
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val stallc = Bool(OUTPUT);
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2012-02-08 08:54:25 +01:00
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val stalld = Bool(OUTPUT);
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2011-10-26 08:02:47 +02:00
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}
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class rocketCtrlSboard extends Component
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{
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override val io = new ioCtrlSboard();
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2012-02-12 02:20:33 +01:00
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val reg_busy = Reg(resetVal = Bits(0, 32));
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2011-10-26 08:02:47 +02:00
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2012-01-02 11:51:30 +01:00
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val set_mask = io.set.toUFix << io.seta;
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val clr_mask = ~(io.clr.toUFix << io.clra);
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2012-02-12 02:20:33 +01:00
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reg_busy := (reg_busy | set_mask) & clr_mask
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2011-10-26 08:02:47 +02:00
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io.stalla := reg_busy(io.raddra).toBool;
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io.stallb := reg_busy(io.raddrb).toBool;
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io.stallc := reg_busy(io.raddrc).toBool;
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2012-02-08 08:54:25 +01:00
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io.stalld := reg_busy(io.raddrd).toBool;
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2011-10-26 08:02:47 +02:00
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}
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