34 lines
1.7 KiB
Markdown
34 lines
1.7 KiB
Markdown
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Rocket Core Generator
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================================================================
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Rocket is a 6-stage single-issue in-order pipeline that executes the 64-bit
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scalar RISC-V ISA. Rocket implements an MMU that supports page-based virtual
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memory and is able to boot modern operating systems such as Linux. Rocket
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also has an optional IEEE 754-2008-compliant FPU, which implements both
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single- and double-precision floating-point operations, including fused
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multiply-add.
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We plan to open-source our Rocket core generator written in Chisel in the near
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future. We are currently in the process of cleaning up the repository. Please stay tuned.
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Currently, a Rocket core with an 8 KB direct-mapped L1 instruction cache
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and an 8 KB direct-mapped L1 data cache has been instantiated and committed to
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the zynq-fpga infrastructure repository. A copy of the generated Verilog is available
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[here](https://raw.githubusercontent.com/ucb-bar/zynq-fpga/master/hw/src/verilog/Slave.v).
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The following table compares a 32-bit ARM Cortex-A5 core to a 64-bit RISC-V
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Rocket core built in the same TSMC process (40GPLUS). Fourth column is the
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ratio of RISC-V Rocket to ARM Cortex-A5. Both use single-instruction-issue,
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in-order pipelines, yet the RISC-V core is faster, smaller, and uses less
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power.
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ISA/Implementation | ARM Cortex-A5 | RISC-V Rocket | R/A
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--- | --- | --- | ---
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ISA Register Width | 32 bits | 64 bits | 2
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Frequency | >1 GHz | >1 GHz | 1
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Dhrystone Performance | 1.57 DMIPS/MHz | 1.72 DMIPS/MHz | 1.1
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Area excluding caches | 0.27 mm<sup>2</sup> | 0.14 mm<sup>2</sup> | 0.5
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Area with 16KB caches | 0.53 mm<sup>2</sup> | 0.39 mm<sup>2</sup> | 0.7
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Area Efficiency | 2.96 DMIPS/MHz/mm<sup>2</sup> | 4.41 DMIPS/MHz/mm<sup>2</sup> | 1.5
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Dynamic Power | <0.08 mW/MHz | 0.034 mW/MHz | >= 0.4
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