73 lines
2.6 KiB
Scala
73 lines
2.6 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import scala.math.max
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import chisel3.internal.sourceinfo.SourceInfo
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case class IntSourceParameters(device: String, num: Int)
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case class IntSinkPortParameters()
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case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
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{
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val num = sources.map(_.num).sum
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}
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
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object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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{
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def edgeO(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
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def edgeI(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
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def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = {
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if (eo.isEmpty) Vec(0, Vec(0, Bool())) else
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Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
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}
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def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
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require (!ei.isEmpty)
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Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip
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}
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def connect(bo: Vec[Bool], eo: IntEdge, bi: Vec[Bool], ei: IntEdge)(implicit sourceInfo: SourceInfo): Unit = {
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require (eo == ei)
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// Cannot use bulk connect, because the widths could differ
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(bo zip bi) foreach { case (o, i) => i := o }
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}
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}
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case class IntIdentityNode() extends IdentityNode(IntImp)
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case class IntOutputNode() extends OutputNode(IntImp)
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case class IntInputNode() extends InputNode(IntImp)
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case class IntSourceNode(device: String, num: Int) extends SourceNode(IntImp)(
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IntSourcePortParameters(Seq(IntSourceParameters(device, num))),
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(if (num == 0) 0 else 1) to 1)
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case class IntSinkNode() extends SinkNode(IntImp)(IntSinkPortParameters())
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case class IntAdapterNode(
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sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
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sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters,
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numSourcePorts: Range.Inclusive = 1 to 1,
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numSinkPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts)
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class IntXbar extends LazyModule
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{
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val intnode = IntAdapterNode(
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numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink?
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numSinkPorts = 1 to 128,
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sourceFn = { seq => IntSourcePortParameters(seq.map(_.sources).flatten) },
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sinkFn = { _ => IntSinkPortParameters() })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = intnode.bundleIn
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val out = intnode.bundleOut
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}
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val cat = (intnode.edgesIn zip io.in).map{ case (e, i) => i.take(e.source.num) }.flatten
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io.out.foreach { _ := cat }
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}
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}
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