2017-07-23 17:31:04 +02:00
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.system
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.devices.tilelink._
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/** Example Top with periphery devices and ports, and a Rocket coreplex */
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class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
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with HasAsyncExtInterrupts
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with HasMasterAXI4MemPort
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with HasMasterAXI4MMIOPort
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with HasSlaveAXI4Port
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with HasPeripheryBootROM
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with HasPeripheryErrorSlave {
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override lazy val module = new ExampleRocketSystemModule(this)
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}
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class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketCoreplexModule(_outer)
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with HasRTCModuleImp
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with HasExtInterruptsModuleImp
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with HasMasterAXI4MemPortModuleImp
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with HasMasterAXI4MMIOPortModuleImp
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with HasSlaveAXI4PortModuleImp
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2017-07-25 20:57:58 +02:00
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with HasPeripheryBootROMModuleImp
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