20 lines
324 B
Coq
20 lines
324 B
Coq
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// You can't divide clocks in Chisel
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module ClockDivider(
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input clock_in,
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input reset_in,
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output clock_out,
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output reset_out
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);
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reg [2:0] shift = 3'b001;
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always @(posedge clock_in)
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begin
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shift <= {shift[0], shift[2:1]};
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end
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assign reset_out = reset_in;
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assign clock_out = shift[0];
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endmodule
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