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rocket-chip/README

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Quick and dirty instructions:
CHECKOUT THE CODE:
git submodule init
git submodule update
cd riscv-gcc-isasim
git submodule init
git submodule update
BUILDING THE TOOLCHAIN:
To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:
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export RISCV=/path/to/riscv/toolchain/installation
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cd riscv-gcc-isasim
./build.sh
To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):
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cd riscv-tests/isa/
make -j
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cd riscv-asmtests-bmarks/riscv-bmarks/
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make -j
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BUILDING THE PROJECT:
To build the C simulator:
cd emulator
make
To build the VCS simulator:
cd vlsi/build/vcs-sim-rtl
make
in either case, you can run a set of assembly tests or simple benchmarks:
make run-asm-tests
make run-vecasm-tests
make run-vecasm-timer-tests
make run-bmarks-test
To build a C simulator that is capable of VCD waveform generation:
cd emulator
make emulator-debug
And to run the assembly tests on the C simulator and generate waveforms:
make run-asm-tests-debug
make run-vecasm-tests-debug
make run-vecasm-timer-tests-debug
make run-bmarks-test-debug
UPDATING TO A NEWER VERSION OF CHISEL:
To grab a newer version of chisel:
git submodule init
git submodule update
cd chisel
git pull origin master
Then, to compile it and install it into the rocket repo:
cd sbt
sbt package
cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib
If you commit a new jar, you must also commit the updated chisel submodule.