58 lines
1.6 KiB
Scala
58 lines
1.6 KiB
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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case object TLBusDelayProbability extends Field[Double](0.0)
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/** Specifies widths of various attachement points in the SoC */
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trait HasTLBusParams {
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val beatBytes: Int
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val blockBytes: Int
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def beatBits: Int = beatBytes * 8
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def blockBits: Int = blockBytes * 8
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def blockBeats: Int = blockBytes / beatBytes
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def blockOffset: Int = log2Up(blockBytes)
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}
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abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters)
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extends SimpleLazyModule with LazyScope with HasTLBusParams {
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val beatBytes = params.beatBytes
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val blockBytes = params.blockBytes
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require(blockBytes % beatBytes == 0)
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protected def inwardNode: TLInwardNode
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protected def outwardNode: TLOutwardNode
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protected def delayNode(implicit p: Parameters): TLNode = {
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val delayProb = p(TLBusDelayProbability)
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if (delayProb > 0.0) {
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TLDelayer(delayProb) :*=* TLBuffer(BufferParams.flow) :*=* TLDelayer(delayProb)
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} else {
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val nodelay = TLIdentityNode()
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nodelay
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}
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}
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protected def to[T](name: String)(body: => T): T = {
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this { LazyScope(s"${busName}To${name}") { body } }
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}
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protected def from[T](name: String)(body: => T): T = {
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this { LazyScope(s"${busName}From${name}") { body } }
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}
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}
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trait HasTLXbarPhy { this: TLBusWrapper =>
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private val xbar = LazyModule(new TLXbar)
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xbar.suggestName(busName)
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protected def inwardNode: TLInwardNode = xbar.node
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protected def outwardNode: TLOutwardNode = xbar.node
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}
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