150 lines
5.5 KiB
Scala
150 lines
5.5 KiB
Scala
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// See LICENSE for license details.
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package rocketchip
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import cde.{Parameters, Dump}
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import junctions._
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import uncore.devices._
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import rocket._
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import rocket.Util._
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import coreplex._
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class RangeManager {
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private var finalized = false
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private val l = collection.mutable.HashMap[String, Int]()
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def add(name: String, element: Int) = { require(!finalized); l += (name -> element) }
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def rangeMap = {
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finalized = true
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l map {
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var sum = 0
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x => { sum += x._2; (x._1 -> (sum-x._2, sum)) }
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}
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}
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def range(name: String) = rangeMap(name)
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def print = {
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rangeMap map { case (name, (start, end)) =>
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println(s"${name} on port ${start}-${end-1}")
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}
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}
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def sum = {
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finalized = true
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l.map(_._2).sum
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}
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}
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class ResourceManager[T] {
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private var finalized = false
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private val l = collection.mutable.ArrayBuffer[T]()
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def add(element: T) = { require(!finalized); l += element }
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def add(list: Seq[T]) = { require(!finalized); l ++= list }
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def get: Seq[T] = { finalized = true; l }
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}
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class GlobalVariable[T] {
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private var assigned = false
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private var variable: T = _
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def assign(value: T) = { require(!assigned); assigned = true; variable = value }
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def get: T = { require(assigned); variable }
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}
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object GenerateGlobalAddrMap {
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def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry]) = {
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lazy val intIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
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require(p(NTiles) == 1) // TODO relax this
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require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
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entries += AddrMapEntry("dmem0", MemRange(0x80000000L, BigInt(p(DataScratchpadSize)), MemAttr(AddrMapProt.RWX)))
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}
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new AddrMap(entries)
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}
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lazy val extIOAddrMap = new AddrMap(
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pDevicesEntries ++ p(ExtMMIOPorts),
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start = BigInt("50000000", 16),
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collapse = true)
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val memBase = 0x80000000L
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val memSize = p(ExtMemSize)
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Dump("MEM_BASE", memBase)
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val intern = AddrMapEntry("int", intIOAddrMap)
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val extern = AddrMapEntry("ext", extIOAddrMap)
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val io = AddrMapEntry("io", AddrMap((intern +: (!extIOAddrMap.isEmpty).option(extern).toSeq):_*))
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val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
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AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*)
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}
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}
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object GenerateConfigString {
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def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
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val addrMap = p(GlobalAddrMap).get
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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val xLen = p(XLen)
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val res = new StringBuilder
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + c.plicKey.pendingBase).toString(16)};\n"
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res append s" ndevs ${c.plicKey.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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res append "};\n"
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if (addrMap contains "mem") {
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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}
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res append "core {\n"
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for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
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val isa = {
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val m = if (p(MulDivKey).nonEmpty) "m" else ""
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val a = if (p(UseAtomics)) "a" else ""
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val f = if (p(FPUKey).nonEmpty) "f" else ""
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val d = if (p(FPUKey).nonEmpty && p(XLen) > 32) "d" else ""
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val s = if (c.hasSupervisor) "s" else ""
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s"rv${p(XLen)}i$m$a$f$d$s"
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}
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (c.hasSupervisor) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append " };\n"
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res append " };\n"
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res append " };\n"
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}
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res append "};\n"
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pDevicesEntries foreach { entry =>
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val region = addrMap("io:ext:" + entry.name)
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res append s"${entry.name} {\n"
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res append s" addr 0x${region.start.toString(16)};\n"
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res append s" size 0x${region.size.toString(16)}; \n"
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res append "}\n"
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}
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res append '\u0000'
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res.toString
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}
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}
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