2017-07-27 23:56:15 +02:00
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.min
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2017-08-08 03:30:38 +02:00
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abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends LazyModule
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2017-07-27 23:56:15 +02:00
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{
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2017-08-08 03:30:38 +02:00
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protected val nodeIn = TLInputNode()
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protected val nodeOut = TLOutputNode()
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2017-07-27 23:56:15 +02:00
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val node = NodeHandle(nodeIn, nodeOut)
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2017-08-08 03:30:38 +02:00
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protected val bar = LazyModule(new TLBusBypassBar)
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protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
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protected val error = LazyModule(new TLError(ErrorParams(everything), beatBytes))
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2017-07-27 23:56:15 +02:00
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bar.node := nodeIn
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error.node := bar.node
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nodeOut := bar.node
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2017-08-08 03:30:38 +02:00
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}
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2017-07-27 23:56:15 +02:00
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2017-08-08 03:30:38 +02:00
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class TLBusBypass(beatBytes: Int)(implicit p: Parameters) extends TLBusBypassBase(beatBytes)
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{
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2017-07-27 23:56:15 +02:00
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = nodeIn.bundleIn
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val out = nodeOut.bundleOut
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val bypass = Bool(INPUT)
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}
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bar.module.io.bypass := io.bypass
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}
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}
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2017-08-08 03:30:38 +02:00
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class TLBusBypassBar(implicit p: Parameters) extends LazyModule
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2017-07-27 23:56:15 +02:00
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{
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// The client only sees the second slave port
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val node = TLNexusNode(
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numClientPorts = 2 to 2 ,
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numManagerPorts = 1 to 1,
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clientFn = { seq => seq(0) },
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managerFn = { seq => seq(1) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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val bypass = Bool(INPUT)
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}
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val in = io.in(0)
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val out0 = io.out(0)
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val out1 = io.out(1)
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val edge = node.edgesIn(0)
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val bce = edge.manager.anySupportAcquireB && edge.client.anySupportProbe
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// We need to be locked to the given bypass direction until all transactions stop
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val flight = RegInit(UInt(0, width = log2Ceil(3*edge.client.endSourceId+1)))
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val bypass = RegInit(io.bypass) // synchronous reset required
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val (a_first, a_last, _) = edge.firstlast(in.a)
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val (b_first, b_last, _) = edge.firstlast(in.b)
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val (c_first, c_last, _) = edge.firstlast(in.c)
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val (d_first, d_last, _) = edge.firstlast(in.d)
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val (e_first, e_last, _) = edge.firstlast(in.e)
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val (a_request, a_response) = (edge.isRequest(in.a.bits), edge.isResponse(in.a.bits))
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val (b_request, b_response) = (edge.isRequest(in.b.bits), edge.isResponse(in.b.bits))
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val (c_request, c_response) = (edge.isRequest(in.c.bits), edge.isResponse(in.c.bits))
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val (d_request, d_response) = (edge.isRequest(in.d.bits), edge.isResponse(in.d.bits))
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val (e_request, e_response) = (edge.isRequest(in.e.bits), edge.isResponse(in.e.bits))
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val a_inc = in.a.fire() && a_first && a_request
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val b_inc = in.b.fire() && b_first && b_request
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val c_inc = in.c.fire() && c_first && c_request
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val d_inc = in.d.fire() && d_first && d_request
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val e_inc = in.e.fire() && e_first && e_request
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val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
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val a_dec = in.a.fire() && a_last && a_response
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val b_dec = in.b.fire() && b_last && b_response
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val c_dec = in.c.fire() && c_last && c_response
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val d_dec = in.d.fire() && d_last && d_response
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val e_dec = in.e.fire() && e_last && e_response
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val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
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val next_flight = flight + PopCount(inc) - PopCount(dec)
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flight := next_flight
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when (next_flight === UInt(0)) { bypass := io.bypass }
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val stall = bypass != io.bypass
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out0.a.valid := !stall && in.a.valid && bypass
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out1.a.valid := !stall && in.a.valid && !bypass
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in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready)
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out0.a.bits := in.a.bits
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out1.a.bits := in.a.bits
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out0.d.ready := in.d.ready && bypass
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out1.d.ready := in.d.ready && !bypass
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in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid)
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// Argh. The Bundles are not identical, so Mux on bits does not work
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in.d.bits.opcode := Mux(bypass, out0.d.bits.opcode, out1.d.bits.opcode)
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in.d.bits.param := Mux(bypass, out0.d.bits.param, out1.d.bits.param)
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in.d.bits.size := Mux(bypass, out0.d.bits.size, out1.d.bits.size)
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in.d.bits.source := Mux(bypass, out0.d.bits.source, out1.d.bits.source)
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in.d.bits.sink := Mux(bypass, out0.d.bits.sink, out1.d.bits.sink)
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in.d.bits.data := Mux(bypass, out0.d.bits.data, out1.d.bits.data)
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in.d.bits.error := Mux(bypass, out0.d.bits.error, out1.d.bits.error)
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if (bce) {
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out0.b.ready := in.b.ready && bypass
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out1.b.ready := in.b.ready && !bypass
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in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid)
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in.b.bits.opcode := Mux(bypass, out0.b.bits.opcode, out1.b.bits.opcode)
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in.b.bits.param := Mux(bypass, out0.b.bits.param, out1.b.bits.param)
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in.b.bits.size := Mux(bypass, out0.b.bits.size, out1.b.bits.size)
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in.b.bits.source := Mux(bypass, out0.b.bits.source, out1.b.bits.source)
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in.b.bits.address:= Mux(bypass, out0.b.bits.address,out1.b.bits.address)
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in.b.bits.mask := Mux(bypass, out0.b.bits.mask, out1.b.bits.mask)
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in.b.bits.data := Mux(bypass, out0.b.bits.data, out1.b.bits.data)
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out0.c.valid := in.c.valid && bypass
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out1.c.valid := in.c.valid && !bypass
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in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready)
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out0.c.bits := in.c.bits
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out1.c.bits := in.c.bits
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out0.e.valid := in.e.valid && bypass
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out1.e.valid := in.e.valid && !bypass
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in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready)
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out0.e.bits := in.e.bits
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out1.e.bits := in.e.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out0.b.ready := Bool(true)
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out0.c.valid := Bool(false)
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out0.e.valid := Bool(false)
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out1.b.ready := Bool(true)
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out1.c.valid := Bool(false)
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out1.e.valid := Bool(false)
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}
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}
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}
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