42 lines
1.3 KiB
Scala
42 lines
1.3 KiB
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.diplomacy._
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import java.nio.{ByteBuffer, ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Size, location and contents of the boot rom. */
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case class BootROMParams(
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address: BigInt = 0x10000,
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size: Int = 0x10000,
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hang: BigInt = 0x10040,
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contentFileName: String)
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case object BootROMParams extends Field[BootROMParams]
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/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
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trait HasPeripheryBootROM extends HasPeripheryBus {
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val dtb: DTB
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private val params = p(BootROMParams)
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private lazy val contents = {
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val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
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val rom = ByteBuffer.wrap(romdata)
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rom.array() ++ dtb.contents
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}
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def resetVector: BigInt = params.hang
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val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
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bootrom.node := pbus.toVariableWidthSlaves
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}
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/** Coreplex will power-on running at 0x10040 (BootROM) */
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trait HasPeripheryBootROMModuleImp extends LazyMultiIOModuleImp
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with HasResetVectorWire {
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val outer: HasPeripheryBootROM
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global_reset_vector := UInt(outer.resetVector, width = resetVectorBits)
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}
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