44 lines
1.4 KiB
Scala
44 lines
1.4 KiB
Scala
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package groundtest
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import Chisel._
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import uncore._
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import cde.{Parameters, Field}
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class CacheFillTest(implicit val p: Parameters) extends GroundTest()(p)
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with HasTileLinkParameters {
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val capacityKb: Int = p("L2_CAPACITY_IN_KB")
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val nblocks = capacityKb * 1024 / p(CacheBlockBytes)
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val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val inflight = Reg(init = Bool(false))
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val active = state === s_prefetch || state === s_retrieve
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val (xact_id, xact_flip) = Counter(io.mem.acquire.fire(), tlMaxClientXacts)
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val (req_block, round_done) = Counter(io.mem.acquire.fire(), nblocks)
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io.mem.acquire.valid := active && !inflight
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io.mem.acquire.bits := Mux(state === s_prefetch,
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GetPrefetch(xact_id, req_block),
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GetBlock(xact_id, req_block))
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io.mem.grant.ready := active
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when (io.mem.acquire.fire()) {
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inflight := Bool(true)
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}
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val last_grant = !io.mem.grant.bits.hasMultibeatData() ||
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io.mem.grant.bits.addr_beat === UInt(tlDataBeats - 1)
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when (io.mem.grant.fire() && last_grant) {
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inflight := Bool(false)
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}
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when (state === s_start) { state := s_prefetch }
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when (state === s_prefetch && round_done) { state := s_retrieve }
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when (state === s_retrieve && round_done) { state := s_finished }
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io.finished := (state === s_finished)
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io.cache.req.valid := Bool(false)
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}
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