riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4746cf00ce
rocket-chip/vsim/Makefrag-verilog

50 lines
2.3 KiB
Plaintext
Raw Normal View History

Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 09:23:31 +02:00
#--------------------------------------------------------------------
# Verilog Generation
#--------------------------------------------------------------------
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
# If I don't mark these as .SECONDARY then make will delete these internal
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
generate BootROM contents from assembly code
2016-08-05 20:07:42 +02:00
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
mkdir -p $(dir $@)
allow configuration to be in separate project from test harness
2016-09-01 19:28:07 +02:00
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
.prm is output of chisel stage, not firrtl stage
2016-06-29 02:34:37 +02:00
$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
mkdir -p $(dir $@)
replace complicated pattern substitutions with automatic variable
2016-06-29 03:30:11 +02:00
$(FIRRTL) -i $< -o $@ -X verilog
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 09:23:31 +02:00
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
echo "\`endif // CONST_VH" >> $@
update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.run: $(output_dir)/% $(simv)
cd $(sim_dir) && $(exec_simv) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.out: $(output_dir)/% $(simv)
cd $(sim_dir) && $(exec_simv) +verbose +max-cycles=$(timeout_cycles) $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.vcd: $(output_dir)/% $(simv_debug)
cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
cd $(sim_dir) && $(exec_simv_debug) +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.saif: $(output_dir)/% $(simv_debug)
cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Fixed run-bmark-tests make target in vsim
2015-09-10 07:37:47 +02:00
run: run-asm-tests run-bmark-tests
run-debug: run-asm-tests-debug run-bmark-tests-debug
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
run-fast: run-asm-tests-fast run-bmark-tests-fast
update for rocket-chip release
2014-09-01 05:26:55 +02:00
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
.PHONY: run-asm-tests run-bmark-tests
.PHONY: run-asm-tests-debug run-bmark-tests-debug
.PHONY: run run-debug run-fast
update for rocket-chip release
2014-09-01 05:26:55 +02:00
junk += $(output_dir)
Copy Permalink