2016-11-19 04:01:36 +01:00
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// See LICENSE for license details.
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package rocket
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import Chisel._
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2016-11-19 04:11:34 +01:00
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import config.{Parameters, Field}
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2016-11-19 04:01:36 +01:00
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import diplomacy._
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import uncore.tilelink2._
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import uncore.agents._
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import uncore.constants._
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import uncore.tilelink.{TLKey, TLId}
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import util.ParameterizedBundle
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case class DCacheConfig(
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nMSHRs: Int = 1,
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nSDQ: Int = 17,
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nRPQ: Int = 16,
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nMMIOs: Int = 1)
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case object DCacheKey extends Field[DCacheConfig]
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trait HasL1HellaCacheParameters extends HasCacheParameters with HasCoreParameters {
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val outerDataBeats = p(TLKey(p(TLId))).dataBeats
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val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
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val refillCyclesPerBeat = outerDataBits/rowBits
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require(refillCyclesPerBeat == 1)
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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val cacheBlockBytes = p(CacheBlockBytes)
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val lgCacheBlockBytes = log2Up(cacheBlockBytes)
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val wordBits = xLen // really, xLen max
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val wordBytes = wordBits/8
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val wordOffBits = log2Up(wordBytes)
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val beatBytes = cacheBlockBytes / outerDataBeats
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val beatWords = beatBytes / wordBytes
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val beatOffBits = log2Up(beatBytes)
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val idxMSB = untagBits-1
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val idxLSB = blockOffBits
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val offsetmsb = idxLSB-1
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val offsetlsb = wordOffBits
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val rowWords = rowBits/wordBits
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val doNarrowRead = coreDataBits * nWays % rowBits == 0
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val encDataBits = code.width(coreDataBits)
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val encRowBits = encDataBits*rowWords
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val nIOMSHRs = 1
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val lrscCycles = 32 // ISA requires 16-insn LRSC sequences to succeed
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require(isPow2(nSets))
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require(rowBits >= coreDataBits)
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require(rowBits <= outerDataBits)
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require(xLen <= outerDataBits) // would need offset addr for puts if data width < xlen
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require(!usingVM || untagBits <= pgIdxBits)
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}
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abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
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with HasL1HellaCacheParameters
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abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasL1HellaCacheParameters
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class L1Metadata(implicit p: Parameters) extends Metadata()(p) with HasL1HellaCacheParameters {
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val coh = new ClientMetadata
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}
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object L1Metadata {
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def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {
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val meta = Wire(new L1Metadata)
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meta.tag := tag
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meta.coh := coh
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meta
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}
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}
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class L1MetaReadReq(implicit p: Parameters) extends MetaReadReq {
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val tag = Bits(width = tagBits)
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override def cloneType = new L1MetaReadReq()(p).asInstanceOf[this.type] //TODO remove
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}
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class L1MetaWriteReq(implicit p: Parameters) extends
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MetaWriteReq[L1Metadata](new L1Metadata)
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trait HasCoreMemOp extends HasCoreParameters {
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val addr = UInt(width = coreMaxAddrBits)
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val tag = Bits(width = dcacheReqTagBits)
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val cmd = Bits(width = M_SZ)
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val typ = Bits(width = MT_SZ)
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}
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trait HasCoreData extends HasCoreParameters {
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val data = Bits(width = coreDataBits)
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}
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class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
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class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
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with HasCoreMemOp
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with HasCoreData {
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val replay = Bool()
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val has_data = Bool()
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val data_word_bypass = Bits(width = coreDataBits)
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val store_data = Bits(width = coreDataBits)
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}
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class AlignmentExceptions extends Bundle {
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val ld = Bool()
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val st = Bool()
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}
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class HellaCacheExceptions extends Bundle {
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val ma = new AlignmentExceptions
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val pf = new AlignmentExceptions
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}
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// interface between D$ and processor/DTLB
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class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Decoupled(new HellaCacheReq)
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val s1_kill = Bool(OUTPUT) // kill previous cycle's req
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val s1_data = Bits(OUTPUT, coreDataBits) // data for previous cycle's req
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val s2_nack = Bool(INPUT) // req from two cycles ago is rejected
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val resp = Valid(new HellaCacheResp).flip
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val replay_next = Bool(INPUT)
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val xcpt = (new HellaCacheExceptions).asInput
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val invalidate_lr = Bool(OUTPUT)
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val ordered = Bool(INPUT)
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}
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abstract class HellaCache(val cfg: DCacheConfig)(implicit val p: Parameters) extends LazyModule {
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val node = TLClientNode(TLClientParameters(
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sourceId = IdRange(0, cfg.nMSHRs + cfg.nMMIOs),
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supportsProbe = TransferSizes(p(CacheBlockBytes))))
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val module: HellaCacheModule
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}
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class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends Bundle {
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val cpu = (new HellaCacheIO).flip
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val ptw = new TLBPTWIO()
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val mem = outer.node.bundleOut
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}
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class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends LazyModuleImp(outer)
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with HasL1HellaCacheParameters {
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implicit val cfg = outer.cfg
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val io = new HellaCacheBundle(outer)
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val edge = outer.node.edgesOut(0)
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val tl_out = io.mem(0)
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/* TODO
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edge.manager.managers.foreach { m =>
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if (m.supportsGet) {
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require (m.supportsGet.contains(TransferSizes(1, tlDataBytes)))
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....etc
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}
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}
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*/
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}
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object HellaCache {
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def apply(cfg: DCacheConfig)(implicit p: Parameters) = {
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if (cfg.nMSHRs == 0) LazyModule(new DCache(cfg))
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else LazyModule(new NonBlockingDCache(cfg))
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}
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}
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