70 lines
2.2 KiB
Scala
70 lines
2.2 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.util.IrrevocableIO
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object TLArbiter
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{
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// (valids, idle) => readys
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type Policy = (Seq[Bool], Bool) => Seq[Bool]
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val lowestIndexFirst: Policy = (valids, idle) =>
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valids.scanLeft(Bool(true))(_ && !_).init
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def apply[T <: Data](policy: Policy)(sink: IrrevocableIO[T], sources: (UInt, IrrevocableIO[T])*) {
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require (sources.size >= 1)
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val pairs = sources.toList
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val beatsIn = pairs.map(_._1)
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val sourcesIn = pairs.map(_._2)
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// The number of beats which remain to be sent
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val beatsLeft = RegInit(UInt(0))
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val idle = beatsLeft === UInt(0)
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// Who wants access to the sink?
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val valids = sourcesIn.map(_.valid)
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// Arbitrate amongst the requests
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val readys = Vec(policy(valids, idle))
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// Which request wins arbitration?
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val winners = Vec((readys zip valids) map { case (r,v) => r&&v })
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// Confirm the policy works properly
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require (readys.size == valids.size)
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// Never two winners
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val prefixOR = winners.scanLeft(Bool(false))(_||_).init
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assert((prefixOR zip winners) map { case (p,w) => !p || !w } reduce {_ && _})
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// If there was any request, there is a winner
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assert (!valids.reduce(_||_) || winners.reduce(_||_))
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// Track remaining beats
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val maskedBeats = (winners zip beatsIn) map { case (w,b) => Mux(w, b, UInt(0)) }
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val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
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val todoBeats = Mux(idle, initBeats, beatsLeft)
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beatsLeft := todoBeats - sink.fire()
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assert (!sink.fire() || todoBeats =/= UInt(0)) // underflow is impoosible
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// The one-hot source granted access in the previous cycle
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val state = RegInit(Vec.fill(sources.size)(Bool(false)))
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val muxState = Mux(idle, winners, state)
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state := muxState
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val ones = Vec.fill(sources.size)(Bool(true))
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val picked = Mux(idle, ones, state)
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sink.valid := Mux1H(picked, valids)
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if (sources.size > 1) {
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val allowed = Mux(idle, readys, state)
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(sourcesIn zip allowed) foreach { case (s, r) =>
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s.ready := sink.ready && r
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}
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} else {
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sourcesIn(0).ready := sink.ready
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}
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sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
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}
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}
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