2016-06-08 10:39:40 +02:00
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#--------------------------------------------------------------------
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# Verilator Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir
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firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
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verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
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verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
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FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
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$(FIRRTL):
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$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
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.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
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2016-06-11 02:46:45 +02:00
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$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
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2016-06-08 10:39:40 +02:00
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)"
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mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
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2016-06-11 02:46:45 +02:00
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$(generated_dir_debug)/%.$(MODEL).$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs)
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2016-06-08 10:39:40 +02:00
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
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mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
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%.v: %.fir $(FIRRTL)
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mkdir -p $(dir $@)
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
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VERILATOR := verilator --cc --exe
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VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=$(MODEL).reset --assert \
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-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
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model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header)
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$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir) -c -o $@ $<
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header_debug)
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$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -c -o $@ $<
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$(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header)
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mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
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$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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$(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d
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mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
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$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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