2014-09-02 22:51:57 +02:00
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package rocketchip
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2014-08-23 10:26:03 +02:00
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import Chisel._
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import uncore._
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import rocket._
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import rocket.Util._
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class DefaultConfig extends ChiselConfig {
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2014-09-06 15:59:14 +02:00
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val topDefinitions:World.TopDefs = {
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2014-08-23 10:26:03 +02:00
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(pname,site,here) => pname match {
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2014-08-25 04:30:53 +02:00
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//HTIF Parameters
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case HTIFWidth => 16
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
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2014-08-23 10:26:03 +02:00
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//Params used by all caches
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case ECCCode => None
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case WordBits => site(XprLen)
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case Replacer => () => new RandomReplacement(site(NWays))
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case BlockOffBits => site(CacheName) match {
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case "L1I" | "L1D" => log2Up(site(TLDataBits)/8)
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case "L2" => 0
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}
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case NSets => site(CacheName) match {
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case "L1I" => 128
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2014-08-25 04:30:53 +02:00
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case "L1D" => Knob("L1D_SETS") //128
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2014-08-23 10:26:03 +02:00
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case "L2" => 512
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}
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case NWays => site(CacheName) match {
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case "L1I" => 2
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2014-08-25 04:30:53 +02:00
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case "L1D" => Knob("L1D_WAYS") //4
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2014-08-23 10:26:03 +02:00
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case "L2" => 8
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}
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case RowBits => site(CacheName) match {
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case "L1I" => 4*site(CoreInstBits)
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case "L1D" => 2*site(CoreDataBits)
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case "L2" => site(TLDataBits)
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}
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//L1InstCache
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case NITLBEntries => 8
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case NBTBEntries => 62
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case NRAS => 2
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//L1DataCache
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case NDTLBEntries => 8
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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2014-08-25 04:30:53 +02:00
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case NMSHRs => Knob("L1D_MSHRS")
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2014-08-23 10:26:03 +02:00
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case LRSCCycles => 32
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//L2CacheParams
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2014-08-25 04:30:53 +02:00
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case NReleaseTransactors => Knob("L2_REL_XACTS")
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case NAcquireTransactors => Knob("L2_ACQ_XACTS")
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2014-08-23 10:26:03 +02:00
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case NClients => site(NTiles) + 1
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//Tile Constants
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
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//Rocket Core Constants
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XprLen => 64
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case NMultXpr => 32
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2014-09-08 02:57:33 +02:00
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case BuildFPU => Some(() => Module(new FPU))
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2014-08-23 10:26:03 +02:00
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XprLen)
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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//Uncore Paramters
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case LNMasters => site(NBanks)
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case LNClients => site(NTiles)+1
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case LNEndpoints => site(LNMasters) + site(LNClients)
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case TLCoherence => site(Coherence)
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case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLMasterXactIdBits => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
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case TLClientXactIdBits => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
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case TLDataBits => site(CacheBlockBytes)*8
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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2014-08-25 04:30:53 +02:00
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case NTiles => Knob("NTILES")
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case NBanks => Knob("NBANKS")
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2014-08-23 10:26:03 +02:00
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case BankIdLSB => 5
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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2014-08-25 04:30:53 +02:00
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case UseBackupMemoryPort => true
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case BuildDRAMSideLLC => (refill: Int) => {
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2014-08-23 10:26:03 +02:00
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if(site[Boolean]("USE_DRAMSIDE_LLC")) {
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val tag = Mem(Bits(width = 152), 512, seqRead = true)
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val data = Mem(Bits(width = 64), 4096, seqRead = true)
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Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
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refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
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} else { Module(new DRAMSideLLCNull(16, refill)) }
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}
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2014-08-25 04:30:53 +02:00
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case BuildCoherenceMaster => (id: Int) => {
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if(site[Boolean]("USE_L2_CACHE")) {
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2014-08-23 10:26:03 +02:00
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Module(new L2HellaCache(id), { case CacheName => "L2" })
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2014-08-25 04:30:53 +02:00
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} else {
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Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
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2014-08-23 10:26:03 +02:00
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}
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}
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case Coherence => {
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val dir = new FullRepresentation(site(NClients))
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val enSharing = site[Boolean]("ENABLE_SHARING")
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val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")
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if(enSharing) {
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if(enCleanEx) new MESICoherence(dir)
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else new MSICoherence(dir)
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} else {
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if(enCleanEx) new MEICoherence(dir)
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else new MICoherence(dir)
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}
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}
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case "ENABLE_SHARING" => true
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case "ENABLE_CLEAN_EXCLUSIVE" => true
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case "USE_DRAMSIDE_LLC" => true
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2014-08-25 04:30:53 +02:00
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case "USE_L2_CACHE" => false
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2014-08-23 10:26:03 +02:00
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}
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}
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2014-09-06 15:59:14 +02:00
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override val knobValues:Any=>Any = {
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2014-08-25 04:30:53 +02:00
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case "NTILES" => 1
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case "NBANKS" => 1
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case "L2_REL_XACTS" => 1
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case "L2_ACQ_XACTS" => 7
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 128
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case "L1D_WAYS" => 4
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}
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2014-08-23 10:26:03 +02:00
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}
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2014-08-28 22:07:54 +02:00
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class DefaultVLSIConfig extends DefaultConfig
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class DefaultCPPConfig extends DefaultConfig
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class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
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2014-09-06 15:59:14 +02:00
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val topDefinitions:World.TopDefs = {
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2014-08-28 22:07:54 +02:00
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(pname,site,here) => pname match {
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case NSets => site(CacheName) match {
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case "L1I" => 64
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case "L1D" => Knob("L1D_SETS")
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}
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case NWays => site(CacheName) match {
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case "L1I" => 1
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case "L1D" => Knob("L1D_WAYS")
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}
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case FastMulDiv => false
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case NITLBEntries => 4
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case NBTBEntries => 8
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case NDTLBEntries => 4
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2014-09-06 15:59:14 +02:00
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case _ => default.topDefinitions(pname,site,here)
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2014-08-28 22:07:54 +02:00
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}
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}
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2014-09-06 15:59:14 +02:00
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override val knobValues:Any=>Any = {
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2014-08-28 22:07:54 +02:00
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case "NTILES" => 1
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case "NBANKS" => 1
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case "L2_REL_XACTS" => 1
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case "L2_ACQ_XACTS" => 7
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 1
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}
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}
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2014-08-23 10:26:03 +02:00
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2014-08-28 22:07:54 +02:00
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class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig)
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