43 lines
1.6 KiB
Scala
43 lines
1.6 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import junctions._
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class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule
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{
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val node = TLIdentityNode()
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val in_clock = Clock(INPUT)
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val in_reset = Bool(INPUT)
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val out = node.bundleOut
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val out_clock = Clock(INPUT)
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val out_reset = Bool(INPUT)
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}
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// Transfer all TL2 bundles from/to the same domains
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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out.a <> AsyncDecoupledCrossing(io.in_clock, io.in_reset, in.a, io.out_clock, io.out_reset, depth, sync)
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in.d <> AsyncDecoupledCrossing(io.out_clock, io.out_reset, out.d, io.in_clock, io.in_reset, depth, sync)
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if (edgeOut.manager.anySupportAcquire && edgeOut.client.anySupportProbe) {
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in.b <> AsyncDecoupledCrossing(io.out_clock, io.out_reset, out.b, io.in_clock, io.in_reset, depth, sync)
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out.c <> AsyncDecoupledCrossing(io.in_clock, io.in_reset, in.c, io.out_clock, io.out_reset, depth, sync)
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out.e <> AsyncDecoupledCrossing(io.in_clock, io.in_reset, in.e, io.out_clock, io.out_reset, depth, sync)
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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}
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