2016-11-28 01:16:37 +01:00
|
|
|
// See LICENSE.SiFive for license details.
|
2016-11-23 00:01:45 +01:00
|
|
|
|
|
|
|
package rocketchip
|
|
|
|
|
|
|
|
import Chisel._
|
2017-04-27 23:51:28 +02:00
|
|
|
import coreplex.RocketPlex
|
|
|
|
import diplomacy.LazyModule
|
2016-11-23 00:01:45 +01:00
|
|
|
|
2017-02-23 23:25:17 +01:00
|
|
|
trait RocketPlexMaster extends HasTopLevelNetworks {
|
2016-11-23 00:01:45 +01:00
|
|
|
val module: RocketPlexMasterModule
|
|
|
|
|
2017-04-27 23:51:28 +02:00
|
|
|
val coreplex = LazyModule(new RocketPlex)
|
2016-11-23 00:01:45 +01:00
|
|
|
|
2017-03-25 05:37:47 +01:00
|
|
|
coreplex.l2in :=* fsb.node
|
|
|
|
bsb.node :*= coreplex.l2out
|
2016-11-23 00:01:45 +01:00
|
|
|
socBus.node := coreplex.mmio
|
|
|
|
coreplex.mmioInt := intBus.intnode
|
2017-02-04 01:55:44 +01:00
|
|
|
|
|
|
|
require (mem.size == coreplex.mem.size)
|
|
|
|
(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
|
2016-11-23 00:01:45 +01:00
|
|
|
}
|
|
|
|
|
2017-02-23 23:25:17 +01:00
|
|
|
trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle {
|
2016-11-23 00:01:45 +01:00
|
|
|
val outer: RocketPlexMaster
|
|
|
|
}
|
|
|
|
|
2017-02-23 23:25:17 +01:00
|
|
|
trait RocketPlexMasterModule extends HasTopLevelNetworksModule {
|
2016-11-23 00:01:45 +01:00
|
|
|
val outer: RocketPlexMaster
|
|
|
|
val io: RocketPlexMasterBundle
|
2017-01-28 02:09:43 +01:00
|
|
|
val clock: Clock
|
|
|
|
val reset: Bool
|
|
|
|
|
|
|
|
outer.coreplex.module.io.tcrs.foreach { case tcr =>
|
|
|
|
tcr.clock := clock
|
|
|
|
tcr.reset := reset
|
|
|
|
}
|
2016-11-23 00:01:45 +01:00
|
|
|
}
|