2016-09-10 02:16:35 +02:00
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.util.LFSR16
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import junctions.unittests._
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2016-09-13 01:55:29 +02:00
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class IDMapGenerator(numIds: Int) extends Module {
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val w = log2Up(numIds)
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val io = new Bundle {
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val free = Decoupled(UInt(width = w)).flip
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val alloc = Decoupled(UInt(width = w))
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}
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// True indicates that the id is available
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val bitmap = RegInit(Vec.fill(numIds){Bool(true)})
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io.free.ready := Bool(true)
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assert(!io.free.valid || !bitmap(io.free.bits)) // No double freeing
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val mask = bitmap.scanLeft(Bool(false))(_||_).init
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val select = mask zip bitmap map { case(m,b) => !m && b }
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io.alloc.bits := OHToUInt(select)
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io.alloc.valid := bitmap.reduce(_||_)
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when (io.alloc.fire()) {
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bitmap(io.alloc.bits) := Bool(false)
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}
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when (io.free.fire()) {
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bitmap(io.free.bits) := Bool(true)
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}
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}
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2016-09-10 02:16:35 +02:00
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object LFSR64
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{
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private var counter = 0
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private def next: Int = {
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counter += 1
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counter
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}
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def apply(increment: Bool = Bool(true), seed: Int = next): UInt =
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{
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val wide = 64
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val lfsr = RegInit(UInt((seed * 0xDEADBEEFCAFEBAB1L) >>> 1, width = wide))
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val xor = lfsr(0) ^ lfsr(1) ^ lfsr(3) ^ lfsr(4)
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when (increment) { lfsr := Cat(xor, lfsr(wide-1,1)) }
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lfsr
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}
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}
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object NoiseMaker
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{
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def apply(wide: Int, increment: Bool = Bool(true)): UInt = {
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val lfsrs = Seq.fill((wide+63)/64) { LFSR64(increment) }
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Cat(lfsrs)(wide-1,0)
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}
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}
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2016-09-13 01:55:29 +02:00
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class TLFuzzer(nOperations: Int, inFlight: Int = 32) extends LazyModule
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2016-09-10 02:16:35 +02:00
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{
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2016-09-13 01:55:29 +02:00
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val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
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2016-09-10 02:16:35 +02:00
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val out = node.bundleOut
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val finished = Bool()
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}
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val out = io.out(0)
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val edge = node.edgesOut(0)
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2016-09-13 01:55:29 +02:00
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val endAddress = edge.manager.maxAddress + 1
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val maxTransfer = edge.manager.maxTransfer
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val beatBytes = edge.manager.beatBytes
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val maxLgBeats = log2Up(maxTransfer/beatBytes)
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val addressBits = log2Up(endAddress)
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val sizeBits = edge.bundle.sizeBits
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val dataBits = edge.bundle.dataBits
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// Progress through operations
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val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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2016-09-13 03:39:50 +02:00
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io.finished := num_resps === UInt(0)
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2016-09-13 01:55:29 +02:00
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// Progress within each operation
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val a = out.a.bits
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val a_beats1 = edge.numBeats1(a)
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val a_counter = RegInit(UInt(0, width = maxLgBeats))
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val a_counter1 = a_counter - UInt(1)
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val a_first = a_counter === UInt(0)
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val a_last = a_counter === UInt(1) || a_beats1 === UInt(0)
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val req_done = out.a.fire() && a_last
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val d = out.d.bits
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val d_beats1 = edge.numBeats1(d)
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val d_counter = RegInit(UInt(0, width = maxLgBeats))
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val d_counter1 = d_counter - UInt(1)
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val d_first = d_counter === UInt(0)
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val d_last = d_counter === UInt(1) || d_beats1 === UInt(0)
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val resp_done = out.d.fire() && d_last
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// Source ID generation
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val idMap = Module(new IDMapGenerator(inFlight))
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val alloc = Queue.irrevocable(idMap.io.alloc, 1, pipe = true)
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val src = alloc.bits
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alloc.ready := req_done
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idMap.io.free.valid := resp_done
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idMap.io.free.bits := out.d.bits.source
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// Increment random number generation for the following subfields
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2016-09-10 02:16:35 +02:00
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val inc = Wire(Bool())
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2016-09-13 01:55:29 +02:00
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val inc_beat = Wire(Bool())
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2016-09-10 02:16:35 +02:00
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val arth_op = NoiseMaker(3, inc)
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val log_op = NoiseMaker(2, inc)
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2016-09-13 01:55:29 +02:00
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val amo_size = UInt(2) + NoiseMaker(1, inc) // word or dword
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val size = NoiseMaker(sizeBits, inc)
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val addr = NoiseMaker(addressBits, inc) & ~UIntToOH1(size, addressBits)
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val mask = NoiseMaker(beatBytes, inc_beat) & edge.mask(addr, size)
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val data = NoiseMaker(dataBits, inc_beat)
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2016-09-10 02:16:35 +02:00
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val (glegal, gbits) = edge.Get(src, addr, size)
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val (pflegal, pfbits) = if(edge.manager.anySupportPutFull) {
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edge.Put(src, addr, size, data)
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} else { (glegal, gbits) }
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val (pplegal, ppbits) = if(edge.manager.anySupportPutPartial) {
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2016-09-13 01:55:29 +02:00
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edge.Put(src, addr, size, data, mask)
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2016-09-10 02:16:35 +02:00
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} else { (glegal, gbits) }
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val (alegal, abits) = if(edge.manager.anySupportArithmetic) {
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edge.Arithmetic(src, addr, size, data, arth_op)
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} else { (glegal, gbits) }
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val (llegal, lbits) = if(edge.manager.anySupportLogical) {
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edge.Logical(src, addr, size, data, log_op)
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} else { (glegal, gbits) }
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val (hlegal, hbits) = if(edge.manager.anySupportHint) {
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edge.Hint(src, addr, size, UInt(0))
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} else { (glegal, gbits) }
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val a_type_sel = NoiseMaker(3, inc)
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val legal = MuxLookup(a_type_sel, glegal, Seq(
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UInt("b000") -> glegal,
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UInt("b001") -> pflegal,
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UInt("b010") -> pplegal,
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UInt("b011") -> alegal,
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UInt("b100") -> llegal,
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UInt("b101") -> hlegal))
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val bits = MuxLookup(a_type_sel, gbits, Seq(
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UInt("b000") -> gbits,
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UInt("b001") -> pfbits,
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UInt("b010") -> ppbits,
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UInt("b011") -> abits,
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UInt("b100") -> lbits,
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UInt("b101") -> hbits))
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2016-09-13 01:55:29 +02:00
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out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
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2016-09-10 02:16:35 +02:00
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out.a.bits := bits
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.d.ready := Bool(true)
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out.e.valid := Bool(false)
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2016-09-13 01:55:29 +02:00
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inc := !legal || req_done
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inc_beat := !legal || out.a.fire()
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2016-09-10 02:16:35 +02:00
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when (out.a.fire()) {
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2016-09-13 01:55:29 +02:00
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a_counter := Mux(a_first, a_beats1, a_counter1)
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when(a_last) { num_reqs := num_reqs - UInt(1) }
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}
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when (out.d.fire()) {
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d_counter := Mux(d_first, d_beats1, d_counter1)
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when(d_last) { num_resps := num_resps - UInt(1) }
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2016-09-10 02:16:35 +02:00
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}
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}
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}
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class TLFuzzRAM extends LazyModule
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{
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2016-09-13 01:55:29 +02:00
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val model = LazyModule(new TLRAMModel)
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2016-09-10 02:16:35 +02:00
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val ram = LazyModule(new TLRAM(AddressSet(0, 0xfff)))
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val xbar = LazyModule(new TLXbar)
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val fuzz = LazyModule(new TLFuzzer(1000))
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2016-09-13 01:55:29 +02:00
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model.node := fuzz.node
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xbar.node := TLWidthWidget(model.node, 16)
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ram.node := TLHintHandler(TLFragmenter(TLBuffer(xbar.node), 4, 256))
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2016-09-10 02:16:35 +02:00
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLFuzzRAMTest extends UnitTest {
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2016-09-13 01:55:29 +02:00
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val dut = Module(LazyModule(new TLFuzzRAM).module)
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2016-09-10 02:16:35 +02:00
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io.finished := dut.io.finished
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}
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