123 lines
4.5 KiB
Scala
123 lines
4.5 KiB
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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class TLRegisterNode(address: AddressSet, beatBytes: Int = 4)
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extends TLManagerNode(beatBytes, TLManagerParameters(
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address = Seq(address),
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))) // requests are handled in order
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{
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require (!address.strided)
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// Calling this method causes the matching TL2 bundle to be
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// configured to route all requests to the listed RegFields.
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def regmap(mapping: RegField.Map*) = {
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val regmap = mapping.toList
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require (!regmap.isEmpty)
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// Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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(offsets zip fields) map { case (o, f) => (reg, o, f) }
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}.flatten
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// Confirm that no register is too big
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require (flat.map(_._2).max <= beatBytes*8)
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// All registers must fit inside the device address space
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val maxIndex = regmap.map(_._1).max
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require (address.mask >= maxIndex*beatBytes)
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// Which register is touched?
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val alignBits = log2Ceil(beatBytes)
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val addressBits = log2Up(maxIndex+1)
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val a = bundleIn(0).a // Must apply Queue !!! (so no change once started)
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val d = bundleIn(0).d
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val regIdx = a.bits.address(addressBits+alignBits-1, alignBits)
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val regSel = UIntToOH(regIdx)
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// What is the access?
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val opcode = a.bits.opcode
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val read = a.valid && opcode === TLMessages.Get
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val write = a.valid && (opcode === TLMessages.PutFullData || opcode === TLMessages.PutPartialData)
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val wmaskWide = Vec.tabulate(beatBytes*8) { i => a.bits.wmask(i/8) } .toBits.asUInt
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val dataIn = a.bits.data & wmaskWide // zero undefined bits
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// The output values for each register
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val dataOutAcc = Array.tabulate(maxIndex+1) { _ => UInt(0) }
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// The ready state for read and write
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val rReadyAcc = Array.tabulate(maxIndex+1) { _ => Bool(true) }
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val wReadyAcc = Array.tabulate(maxIndex+1) { _ => Bool(true) }
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// Apply all the field methods
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flat.foreach { case (reg, low, field) =>
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val high = low + field.width - 1
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val rfire = wmaskWide(high, low).orR()
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val wfire = wmaskWide(high, low).andR()
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val sel = regSel(reg)
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val ren = read && sel && rfire
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val wen = write && sel && wfire
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val (rReady, rResult) = field.read(ren)
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val wReady = field.write(wen, dataIn(high, low))
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dataOutAcc(reg) = dataOutAcc(reg) | (rResult << low)
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rReadyAcc(reg) = rReadyAcc(reg) && (!rfire || rReady)
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wReadyAcc(reg) = wReadyAcc(reg) && (!wfire || wReady)
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}
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// Create the output data signal
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val dataOut = Vec(dataOutAcc)(regIdx)
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val rReady = Vec(rReadyAcc)(regIdx)
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val wReady = Vec(wReadyAcc)(regIdx)
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val ready = (read && rReady) || (write && wReady)
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a.ready := ready && d.ready
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d.valid := a.valid && ready
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val edge = edgesIn(0)
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d.bits := edge.AccessAck(a.bits.source, a.bits.size)
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// avoid a Mux on the data bus by manually overriding two fields
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d.bits.data := dataOut
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d.bits.opcode := Mux(opcode === TLMessages.Get, TLMessages.AccessAck, TLMessages.AccessAckData)
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}
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}
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object TLRegisterNode
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{
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def apply(address: AddressSet, beatBytes: Int = 4) = new TLRegisterNode(address, beatBytes)
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}
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// These convenience methods below combine to make it possible to create a TL2
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// register mapped device from a totally abstract register mapped device.
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// See GPIO.scala in this directory for an example
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abstract class TLRegFactory(address: AddressSet, beatBytes: Int) extends TLFactory
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{
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val node = TLRegisterNode(address, beatBytes)
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}
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class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle
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class TLRegModule[P, B <: Bundle](val params: P, val io: B, factory: TLRegFactory)
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extends TLModule(factory) with HasRegMap
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{
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def regmap(mapping: RegField.Map*) = factory.node.regmap(mapping:_*)
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}
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class TLRegisterRouter[B <: Bundle, M <: TLModule]
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(address: Option[BigInt] = None, size: BigInt = 4096, beatBytes: Int = 4)
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(bundleBuilder: Vec[TLBundle] => B)
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(moduleBuilder: (B, TLRegFactory) => M)
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extends TLRegFactory(AddressSet(size-1, address), beatBytes)
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{
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require (size % 4096 == 0) // devices should be 4K aligned
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require (isPow2(size))
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require (size >= 4096)
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lazy val module = Module(moduleBuilder(bundleBuilder(node.bundleIn), this))
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}
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