2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2013-01-25 08:56:45 +01:00
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#ifndef _HTIF_EMULATOR_H
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#define _HTIF_EMULATOR_H
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#include <fesvr/htif_pthread.h>
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class htif_emulator_t : public htif_pthread_t
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{
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2016-02-18 00:23:30 +01:00
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int memory_channel_mux_select;
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2013-01-25 08:56:45 +01:00
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public:
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2016-05-01 05:59:36 +02:00
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htif_emulator_t(const std::vector<std::string>& args)
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2016-02-18 00:23:30 +01:00
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: htif_pthread_t(args),
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memory_channel_mux_select(0)
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2013-01-25 08:56:45 +01:00
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{
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2016-02-18 00:23:30 +01:00
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for (const auto& arg: args) {
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if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27))
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memory_channel_mux_select = atoi(arg.c_str()+27);
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}
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}
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2013-01-25 08:56:45 +01:00
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void set_clock_divisor(int divisor, int hold_cycles)
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{
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2016-02-26 06:57:37 +01:00
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#ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET
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2016-02-23 00:30:19 +01:00
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/* We only want to write the HTIF clock divisor SCR on targets where it
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* actually exists (there isn't one on the FPGA, for example). */
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2016-02-26 06:57:37 +01:00
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write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET, divisor | hold_cycles << 16);
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2016-02-23 00:30:19 +01:00
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#endif
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2013-01-25 08:56:45 +01:00
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}
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void start()
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{
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set_clock_divisor(5, 2);
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htif_pthread_t::start();
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}
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};
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#endif
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