57 lines
1.7 KiB
Scala
57 lines
1.7 KiB
Scala
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// See LICENSE.SiFive for license details.
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package uncore.tilelink2
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import Chisel._
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import config._
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import diplomacy._
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import util._
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class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
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{
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val device = new SimpleDevice("error-device", Seq("sifive,error0"))
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = address,
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resources = device.reg,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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supportsArithmetic = TransferSizes(1, beatBytes),
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supportsLogical = TransferSizes(1, beatBytes),
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supportsHint = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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minLatency = 1))) // no bypass needed for this device
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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import TLMessages._
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val opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck)
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val in = io.in(0)
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val a = Queue(in.a, 1)
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val d = in.d
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a.ready := d.ready
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d.valid := a.valid
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d.bits.opcode := opcodes(a.bits.opcode)
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d.bits.param := UInt(0)
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d.bits.size := a.bits.size
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d.bits.source := a.bits.source
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d.bits.sink := UInt(0)
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d.bits.addr_lo := a.bits.address
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d.bits.data := UInt(0)
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d.bits.error := a.bits.opcode =/= Hint // Hints may not error
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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