25 lines
802 B
Scala
25 lines
802 B
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.diplomacy.LazyMultiIOModuleImp
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import freechips.rocketchip.devices.tilelink.HasPeripheryClint
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/** Real-time clock is based on RTCPeriod relative to system clock.
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*/
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case object RTCPeriod extends Field[Option[Int]]
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trait HasRTCModuleImp extends LazyMultiIOModuleImp {
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val outer: HasPeripheryClint
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private val internalPeriod: Option[Int] = outer.p(RTCPeriod)
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require(internalPeriod.isDefined, "RTCPeriod is not defined")
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// Use the static period to toggle the RTC
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val (rtc_counter, _) = Counter(true.B, internalPeriod.get)
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val tick = rtc_counter(log2Up(internalPeriod.get)-1)
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outer.clint.module.io.rtcTick := tick
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}
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