2016-11-16 03:27:52 +01:00
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package coreplex
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import Chisel._
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2016-11-18 23:05:14 +01:00
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import config._
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2016-11-16 03:27:52 +01:00
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import diplomacy._
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import uncore.tilelink2._
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import uncore.coherence._
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import rocket._
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import uncore.devices.NTiles
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trait RocketPlex extends CoreplexRISCVPlatform {
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val module: RocketPlexModule
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val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) }
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val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
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tileIntNodes.foreach { _ := plic.intnode }
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rocketTiles.foreach { r =>
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r.slaveNode.foreach { _ := cbus.node }
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l1tol2.node := r.cachedOut
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l1tol2.node := r.uncachedOut
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}
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}
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trait RocketPlexBundle extends CoreplexRISCVPlatformBundle {
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val outer: CoreplexRISCVPlatform
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}
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trait RocketPlexModule extends CoreplexRISCVPlatformModule {
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val outer: RocketPlex
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val io: RocketPlexBundle
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outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
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tile.io.hartid := UInt(i)
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tile.io.resetVector := io.resetVector
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tile.io.interrupts := outer.clint.module.io.tiles(i)
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tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.io.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0)
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tile.io.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1))
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}
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}
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