#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------

# Verilog sources

bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
	$(base_dir)/vsrc/jtag_vpi.v \
	$(base_dir)/vsrc/AsyncMailbox.v \
	$(base_dir)/vsrc/AsyncResetReg.v

sim_vsrcs = \
	$(generated_dir)/$(MODEL).$(CONFIG).v \
	$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
	$(generated_dir)/consts.$(CONFIG).vh \
	$(base_dir)/vsrc/$(TB).v \
	$(base_dir)/vsrc/SimDTM.v \
	$(bb_vsrcs)

# C sources

sim_csrcs = \
	$(base_dir)/csrc/SimDTM.cc \
	$(base_dir)/csrc/jtag_vpi.c

#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------

verilog: $(sim_vsrcs)

.PHONY: verilog

#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------

VCS = vcs -full64

VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
	+rad +v2k +vcs+lic+wait \
	+vc+list -CC "-I$(VCS_HOME)/include" \
	-CC "-I$(RISCV)/include" \
	-CC "-std=c++11" \
	-CC "-Wl,-rpath,$(RISCV)/lib" \
	-CC "-include $(consts_header)" \
	$(RISCV)/lib/libfesvr.so \
	-sverilog \
	+incdir+$(generated_dir) \
	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
	+define+PRINTF_COND=$(TB).printf_cond \
	+define+STOP_COND=!$(TB).reset \
	+define+RANDOMIZE_MEM_INIT \
	+define+RANDOMIZE_REG_INIT \
	+define+RANDOMIZE_GARBAGE_ASSIGN \
	+define+RANDOMIZE_INVALID_ASSIGN \
	+libext+.v \

VCS_OPTS += +vpi
VCS_OPTS += -P $(base_dir)/vsrc/jtag_vpi.tab
VCS_OPTS += -CC "-DVCS_VPI"


#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------

simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
	cd $(sim_dir) && \
	rm -rf csrc && \
	$(VCS) $(VCS_OPTS) -o $(simv) \
	-debug_pp \

simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
	cd $(sim_dir) && \
	rm -rf csrc && \
	$(VCS) $(VCS_OPTS) -o $(simv_debug) \
	+define+DEBUG -debug_pp \

#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------

seed = $(shell date +%s)
exec_simv = $(simv) -q +ntb_random_seed_automatic
exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
