56 lines
1.7 KiB
Scala
56 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package sifive.freedom.unleashed.u500ml507devkit.fpga
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class MemoryML507Params(
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address: Seq[AddressSet]
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)
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case object MemoryML507Key extends Field[MemoryML507Params]
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trait HasMemoryML507 { this: BaseSubsystem =>
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val memory = LazyModule(new TLMemoryML507(p(MemoryML507Key)))
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// TODO: right TL/memory node chain?
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memory.node := memBuses.head.toDRAMController(Some("ml507mig"))()
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}
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class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyModule {
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val width = 512
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val beatBytes = width/8 // TODO: To wide? TLFragmenter? fixedSize?
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val device = new MemoryDevice
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val node = TLManagerNode(
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Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = c.address,
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resources = device.reg,
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0) // in-order
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)),
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beatBytes = beatBytes
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))
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)
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lazy val module = new LazyModuleImp(this) {
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val (in, edge)= node.in(0)
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// Tie off unused channels
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in.a.ready := Bool(true)
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.d.valid := Bool(false)
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in.e.ready := Bool(true)
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}
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}
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