107 lines
2.8 KiB
Makefile
107 lines
2.8 KiB
Makefile
# See LICENSE for license details.
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# Required variables:
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# - MODEL
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# - PROJECT
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# - CONFIG_PROJECT
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# - CONFIG
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# - BUILD_DIR
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# - FPGA_DIR
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# Optional variables:
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# - EXTRA_FPGA_VSRCS
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# export to bootloader
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export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
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# export to fpga-shells
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export FPGA_TOP_SYSTEM=$(MODEL)
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export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
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export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
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export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
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export BUILD_DIR
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EXTRA_FPGA_VSRCS ?=
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PATCHVERILOG ?= ""
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BOOTROM_DIR ?= ""
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base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
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export rocketchip_dir := $(base_dir)/rocket-chip
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SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
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# Build firrtl.jar and put it where chisel3 can find it.
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FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
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FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
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$(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
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$(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
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touch $(FIRRTL_JAR)
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mkdir -p $(rocketchip_dir)/lib
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cp -p $(FIRRTL_JAR) rocket-chip/lib
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mkdir -p $(rocketchip_dir)/chisel3/lib
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cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
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# Build .fir
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firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
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$(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(SBT) "runMain freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
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.PHONY: firrtl
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firrtl: $(firrtl)
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# Build .v
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verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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$(verilog): $(firrtl) $(FIRRTL_JAR)
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$(FIRRTL) -i $(firrtl) -o $@ -X verilog
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ifneq ($(PATCHVERILOG),"")
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$(PATCHVERILOG)
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endif
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.PHONY: verilog
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verilog: $(verilog)
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romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
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$(romgen): $(verilog) $(BOOTROM_DIR)
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ifneq ($(BOOTROM_DIR),"")
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$(MAKE) -C $(BOOTROM_DIR) romgen
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mv $(BUILD_DIR)/rom.v $@
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endif
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.PHONY: romgen
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romgen: $(romgen)
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f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
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$(f):
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echo $(VSRCS) > $@
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bit := $(BUILD_DIR)/obj/$(MODEL).bit
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$(bit): $(romgen) $(f)
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cd $(BUILD_DIR); vivado \
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-nojournal -mode batch \
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-source $(fpga_common_script_dir)/vivado.tcl \
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-tclargs \
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-top-module "$(MODEL)" \
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-F "$(f)" \
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-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
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-board "$(BOARD)"
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# Build .mcs
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mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
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$(mcs): $(bit)
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cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
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.PHONY: mcs
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mcs: $(mcs)
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# Clean
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.PHONY: clean
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clean:
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ifneq ($(BOOTROM_DIR),"")
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$(MAKE) -C $(BOOTROM_DIR) clean
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endif
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$(MAKE) -C $(FPGA_DIR) clean
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rm -rf $(BUILD_DIR)
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