// See LICENSE.SiFive for license details.

package sifive.freedom.unleashed.u500ml507devkit.fpga

import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

case class MemoryML507Params(
    address: Seq[AddressSet]
)

case object MemoryML507Key extends Field[MemoryML507Params]

trait HasMemoryML507 { this: BaseSubsystem =>
    val memory = LazyModule(new TLMemoryML507(p(MemoryML507Key)))

    // TODO: right TL/memory node chain?
    memory.node := memBuses.head.toDRAMController(Some("ml507mig"))()
}

class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyModule {
    val width = 512
    val beatBytes = width/8 // TODO: To wide? TLFragmenter? fixedSize?

    val device = new MemoryDevice
    val node = TLManagerNode(
        Seq(TLManagerPortParameters(
            Seq(TLManagerParameters(
                address         = c.address,
                resources       = device.reg,
                regionType      = RegionType.UNCACHED,
                executable      = true,
                supportsGet     = TransferSizes(1, beatBytes),
                supportsPutFull = TransferSizes(1, beatBytes),
                fifoId          = Some(0) // in-order
            )),
            beatBytes = beatBytes
        ))
    )

    lazy val module = new LazyModuleImp(this) {
        val (in, edge)= node.in(0)

        // Tie off unused channels
        in.a.ready := Bool(true)
        in.b.valid := Bool(false)
        in.c.ready := Bool(true)
        in.d.valid := Bool(false)
        in.e.ready := Bool(true)
    }
}