riscv/freedom
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base: riscv:552553e526989681e7da3b840518b6f415117514
Branches Tags
riscv:ml507
riscv:boot-test
riscv:master
..
compare: riscv:c812a8878fab68cccb85e26abb9ca30dfa1bb93d
Branches Tags
riscv:ml507
riscv:boot-test
riscv:master

No commits in common. "552553e526989681e7da3b840518b6f415117514" and "c812a8878fab68cccb85e26abb9ca30dfa1bb93d" have entirely different histories.
552553e526 ... c812a8878f

2 changed files with 3 additions and 7 deletions
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8
bootrom/sdboot/sd.c
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@ -10,11 +10,7 @@
#define MAX_CORES 8 #define MAX_CORES 8
//#define PAYLOAD_START 0 #define PAYLOAD_SIZE (16 << 11)
//#define PAYLOAD_CRC7 0xE1
#define PAYLOAD_START 2048
#define PAYLOAD_CRC7 0x51
#define PAYLOAD_SIZE (16 << 12)
#define F_CLK 60000000UL #define F_CLK 60000000UL
@ -167,7 +163,7 @@ static int copy(void)
kprintf("LOADING "); kprintf("LOADING ");
REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL); REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL);
if (sd_cmd(0x52, PAYLOAD_START, PAYLOAD_CRC7) != 0x00) { if (sd_cmd(0x52, 0, 0xE1) != 0x00) {
sd_cmd_end(); sd_cmd_end();
return 1; return 1;
} }

2
common.mk
View File

@ -63,7 +63,7 @@ endif
verilog: $(verilog) verilog: $(verilog)
romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
$(romgen): $(verilog) $(BOOTROM_DIR) $(romgen): $(verilog)
ifneq ($(BOOTROM_DIR),"") ifneq ($(BOOTROM_DIR),"")
$(MAKE) -C $(BOOTROM_DIR) romgen $(MAKE) -C $(BOOTROM_DIR) romgen
mv $(BUILD_DIR)/rom.v $@ mv $(BUILD_DIR)/rom.v $@