Updates to Freedom SoCs

2017-08-18 18:21:04 -07:00 · 2017-08-18 18:21:04 -07:00 · ec70d85cbc
commit ec70d85cbc
parent f4375c2266
64 changed files with 1713 additions and 3449 deletions
--- a/.gitmodules
+++ b/.gitmodules
@ -4,3 +4,6 @@
 [submodule "sifive-blocks"]
 	path = sifive-blocks
 	url = https://github.com/sifive/sifive-blocks.git
 [submodule "fpga-shells"]
 	path = fpga-shells
 	url = https://github.com/sifive/fpga-shells
--- a/Makefile.e300artydevkit
+++ b/Makefile.e300artydevkit
@ -1,17 +1,22 @@
 # See LICENSE for license details.
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 BUILD_DIR := $(base_dir)/builds/e300artydevkit
-FPGA_DIR := $(base_dir)/fpga/e300artydevkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
-MODEL := E300ArtyDevKitTop
+MODEL := E300ArtyDevKitFPGAChip
 PROJECT := sifive.freedom.everywhere.e300artydevkit
 CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
-CONFIG := E300ArtyDevKitConfig
+export CONFIG := E300ArtyDevKitConfig
 export BOARD := arty
 export BOOTROM_DIR := $(base_dir)/bootrom/xip
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
-EXTRA_FPGA_VSRCS := \
+VSRCS := \
 	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
-	$(sifiveblocks_dir)/vsrc/SRLatch.v
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
 	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
 	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
 	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
 include common.mk
--- a/Makefile.u500vc707devkit
+++ b/Makefile.u500vc707devkit
@ -1,39 +1,24 @@
 # See LICENSE for license details.
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 BUILD_DIR := $(base_dir)/builds/u500vc707devkit
-FPGA_DIR := $(base_dir)/fpga/u500vc707devkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
-MODEL := U500VC707DevKitTop
+MODEL := U500VC707DevKitFPGAChip
 PROJECT := sifive.freedom.unleashed.u500vc707devkit
 CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit
-CONFIG := U500VC707DevKitConfig
+export CONFIG := U500VC707DevKitConfig
 export BOARD := vc707
 export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
-EXTRA_FPGA_VSRCS := \
+VSRCS := \
 	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
-	$(sifiveblocks_dir)/vsrc/vc707reset.v
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
-
+	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
-PATCHVERILOG = \
+	$(FPGA_DIR)/$(BOARD)/vsrc/vc707reset.v \
-sed -i -s "s/ *output\(.*\)__inout\(.*\)/inout \1__inout\2/g" $@ && \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
-grep -q -F   "    .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq)," $@ && \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
 sed -i -s  "s/    .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq),/    .io_xilinxvc707mig__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" $@ && \
 grep -q -F   "    .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n)," $@ && \
 sed -i -s  "s/    .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n),/    .io_xilinxvc707mig__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" $@ && \
 grep -q -F   "    .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p)," $@ && \
 sed -i -s  "s/    .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p),/    .io_xilinxvc707mig__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p),/g" $@ && \
 grep -q -F   "    .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq)," $@ && \
 sed -i -s  "s/    .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq),/    .io_port__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" $@ && \
 grep -q -F   "    .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n)," $@ && \
 sed -i -s  "s/    .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n),/    .io_port__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" $@ && \
 grep -q -F   "    .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)" $@ && \
 sed -i -s  "s/    .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)/    .io_port__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p)/g" $@ && \
 grep -q -F   "   .ddr3_dq(blackbox_ddr3_dq)," $@ && \
 sed -i -s  "s/   .ddr3_dq(blackbox_ddr3_dq),/   .ddr3_dq(io_port__inout_ddr3_dq),/g" $@ && \
 grep -q -F   "   .ddr3_dqs_n(blackbox_ddr3_dqs_n)," $@ && \
 sed -i -s  "s/   .ddr3_dqs_n(blackbox_ddr3_dqs_n),/   .ddr3_dqs_n(io_port__inout_ddr3_dqs_n),/g" $@ && \
 grep -q -F   "   .ddr3_dqs_p(blackbox_ddr3_dqs_p)," $@ && \
 sed -i -s  "s/   .ddr3_dqs_p(blackbox_ddr3_dqs_p),/   .ddr3_dqs_p(io_port__inout_ddr3_dqs_p),/g" $@ 
 include common.mk
--- a/bootrom/e300artydevkit.img
+++ b/bootrom/e300artydevkit.img
--- a/bootrom/sdboot/Makefile
+++ b/bootrom/sdboot/Makefile
@ -0,0 +1,47 @@
 # RISCV environment variable must be set
 CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
 OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
 CFLAGS=-march=rv64imac -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles 
 CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 
 CFLAGS+= -I $(BOOTROM_DIR)/include -I.
 LFLAGS=-static -nostdlib -L $(BOOTROM_DIR)/linker -T sdboot.elf.lds
 dtb := $(BUILD_DIR)/$(CONFIG).dtb
 $(dtb): $(BUILD_DIR)/$(CONFIG).dts
 	dtc -I dts -O dtb -o $@ $<
 .PHONY: dtb
 dtb: $(dtb)
 elf := $(BUILD_DIR)/sdboot.elf
 $(elf): $(dtb) head.S kprintf.c sd.c 
 	$(CC) $(CFLAGS) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ head.S sd.c kprintf.c
 .PHONY: elf
 elf: $(elf)
 bin := $(BUILD_DIR)/sdboot.bin
 $(bin): $(elf)
 	$(OBJCOPY) -O binary $< $@
 .PHONY: bin
 bin: $(bin)
 hex := $(BUILD_DIR)/sdboot.hex
 $(hex): $(bin)
 	od -t x4 -An -w4 -v $< > $@
 .PHONY: hex
 hex: $(hex)
 romgen := $(BUILD_DIR)/rom.v
 $(romgen): $(hex)
 	$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
 .PHONY: romgen
 romgen: $(romgen)
 .PHONY: clean
 clean::
 	rm -rf $(hex) $(elf)
--- a/bootrom/sdboot/common.h
+++ b/bootrom/sdboot/common.h
@ -0,0 +1,9 @@
 #ifndef _SDBOOT_COMMON_H
 #define _SDBOOT_COMMON_H
 #ifndef PAYLOAD_DEST
  #define PAYLOAD_DEST MEMORY_MEM_ADDR
 #endif
 #endif
--- a/bootrom/sdboot/head.S
+++ b/bootrom/sdboot/head.S
@ -0,0 +1,18 @@
 // See LICENSE for license details.
 #include <platform.h>
 #include "common.h"
  .section .text.init
  .option norvc
  .globl _prog_start
 _prog_start:
  li sp, (PAYLOAD_DEST + 0x7fff000)
  call main
  csrr a0, mhartid
  la a1, dtb
  li s1, PAYLOAD_DEST
  jr s1
  .section .rodata
 dtb:
  .incbin DEVICE_TREE
--- a/bootrom/sdboot/include/bits.h
+++ b/bootrom/sdboot/include/bits.h
@ -0,0 +1,36 @@
 // See LICENSE for license details.
 #ifndef _RISCV_BITS_H
 #define _RISCV_BITS_H
 #define likely(x) __builtin_expect((x), 1)
 #define unlikely(x) __builtin_expect((x), 0)
 #define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
 #define ROUNDDOWN(a, b) ((a)/(b)*(b))
 #define MAX(a, b) ((a) > (b) ? (a) : (b))
 #define MIN(a, b) ((a) < (b) ? (a) : (b))
 #define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
 #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
 #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
 #define STR(x) XSTR(x)
 #define XSTR(x) #x
 #if __riscv_xlen == 64
 # define SLL32    sllw
 # define STORE    sd
 # define LOAD     ld
 # define LWU      lwu
 # define LOG_REGBYTES 3
 #else
 # define SLL32    sll
 # define STORE    sw
 # define LOAD     lw
 # define LWU      lw
 # define LOG_REGBYTES 2
 #endif
 #define REGBYTES (1 << LOG_REGBYTES)
 #endif
--- a/bootrom/sdboot/include/const.h
+++ b/bootrom/sdboot/include/const.h
@ -0,0 +1,18 @@
 // See LICENSE for license details.
 /* Derived from <linux/const.h> */
 #ifndef _SIFIVE_CONST_H
 #define _SIFIVE_CONST_H
 #ifdef __ASSEMBLER__
 #define _AC(X,Y)        X
 #define _AT(T,X)        X
 #else
 #define _AC(X,Y)        (X##Y)
 #define _AT(T,X)        ((T)(X))
 #endif /* !__ASSEMBLER__*/
 #define _BITUL(x)       (_AC(1,UL) << (x))
 #define _BITULL(x)      (_AC(1,ULL) << (x))
 #endif /* _SIFIVE_CONST_H */
--- a/bootrom/sdboot/include/devices/clint.h
+++ b/bootrom/sdboot/include/devices/clint.h
@ -0,0 +1,14 @@
 // See LICENSE for license details.
 #ifndef _SIFIVE_CLINT_H
 #define _SIFIVE_CLINT_H
 #define CLINT_MSIP 0x0000
 #define CLINT_MSIP_size   0x4
 #define CLINT_MTIMECMP 0x4000
 #define CLINT_MTIMECMP_size 0x8
 #define CLINT_MTIME 0xBFF8
 #define CLINT_MTIME_size 0x8
 #endif /* _SIFIVE_CLINT_H */ 
--- a/bootrom/sdboot/include/devices/gpio.h
+++ b/bootrom/sdboot/include/devices/gpio.h
@ -0,0 +1,24 @@
 // See LICENSE for license details.
 #ifndef _SIFIVE_GPIO_H
 #define _SIFIVE_GPIO_H
 #define GPIO_INPUT_VAL  (0x00)
 #define GPIO_INPUT_EN   (0x04)
 #define GPIO_OUTPUT_EN  (0x08)
 #define GPIO_OUTPUT_VAL (0x0C)
 #define GPIO_PULLUP_EN  (0x10)
 #define GPIO_DRIVE      (0x14)
 #define GPIO_RISE_IE    (0x18)
 #define GPIO_RISE_IP    (0x1C)
 #define GPIO_FALL_IE    (0x20)
 #define GPIO_FALL_IP    (0x24)
 #define GPIO_HIGH_IE    (0x28)
 #define GPIO_HIGH_IP    (0x2C)
 #define GPIO_LOW_IE     (0x30)
 #define GPIO_LOW_IP     (0x34)
 #define GPIO_IOF_EN     (0x38)
 #define GPIO_IOF_SEL    (0x3C)
 #define GPIO_OUTPUT_XOR    (0x40)
 #endif /* _SIFIVE_GPIO_H */
--- a/bootrom/sdboot/include/devices/plic.h
+++ b/bootrom/sdboot/include/devices/plic.h
@ -0,0 +1,31 @@
 // See LICENSE for license details.
 #ifndef PLIC_H
 #define PLIC_H
 #include <const.h>
 // 32 bits per source
 #define PLIC_PRIORITY_OFFSET            _AC(0x0000,UL)
 #define PLIC_PRIORITY_SHIFT_PER_SOURCE  2
 // 1 bit per source (1 address)
 #define PLIC_PENDING_OFFSET             _AC(0x1000,UL)
 #define PLIC_PENDING_SHIFT_PER_SOURCE   0
 //0x80 per target
 #define PLIC_ENABLE_OFFSET              _AC(0x2000,UL)
 #define PLIC_ENABLE_SHIFT_PER_TARGET    7
 #define PLIC_THRESHOLD_OFFSET           _AC(0x200000,UL)
 #define PLIC_CLAIM_OFFSET               _AC(0x200004,UL)
 #define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
 #define PLIC_CLAIM_SHIFT_PER_TARGET     12
 #define PLIC_MAX_SOURCE                 1023
 #define PLIC_SOURCE_MASK                0x3FF
 #define PLIC_MAX_TARGET                 15871
 #define PLIC_TARGET_MASK                0x3FFF
 #endif /* PLIC_H */
--- a/bootrom/sdboot/include/devices/spi.h
+++ b/bootrom/sdboot/include/devices/spi.h
@ -0,0 +1,79 @@
 // See LICENSE for license details.
 #ifndef _SIFIVE_SPI_H
 #define _SIFIVE_SPI_H
 /* Register offsets */
 #define SPI_REG_SCKDIV          0x00
 #define SPI_REG_SCKMODE         0x04
 #define SPI_REG_CSID            0x10
 #define SPI_REG_CSDEF           0x14
 #define SPI_REG_CSMODE          0x18
 #define SPI_REG_DCSSCK          0x28
 #define SPI_REG_DSCKCS          0x2a
 #define SPI_REG_DINTERCS        0x2c
 #define SPI_REG_DINTERXFR       0x2e
 #define SPI_REG_FMT             0x40
 #define SPI_REG_TXFIFO          0x48
 #define SPI_REG_RXFIFO          0x4c
 #define SPI_REG_TXCTRL          0x50
 #define SPI_REG_RXCTRL          0x54
 #define SPI_REG_FCTRL           0x60
 #define SPI_REG_FFMT            0x64
 #define SPI_REG_IE              0x70
 #define SPI_REG_IP              0x74
 /* Fields */
 #define SPI_SCK_POL             0x1
 #define SPI_SCK_PHA             0x2
 #define SPI_FMT_PROTO(x)        ((x) & 0x3)
 #define SPI_FMT_ENDIAN(x)       (((x) & 0x1) << 2)
 #define SPI_FMT_DIR(x)          (((x) & 0x1) << 3)
 #define SPI_FMT_LEN(x)          (((x) & 0xf) << 16)
 /* TXCTRL register */
 #define SPI_TXWM(x)             ((x) & 0xffff)
 /* RXCTRL register */
 #define SPI_RXWM(x)             ((x) & 0xffff)
 #define SPI_IP_TXWM             0x1
 #define SPI_IP_RXWM             0x2
 #define SPI_FCTRL_EN            0x1
 #define SPI_INSN_CMD_EN         0x1
 #define SPI_INSN_ADDR_LEN(x)    (((x) & 0x7) << 1)
 #define SPI_INSN_PAD_CNT(x)     (((x) & 0xf) << 4)
 #define SPI_INSN_CMD_PROTO(x)   (((x) & 0x3) << 8)
 #define SPI_INSN_ADDR_PROTO(x)  (((x) & 0x3) << 10)
 #define SPI_INSN_DATA_PROTO(x)  (((x) & 0x3) << 12)
 #define SPI_INSN_CMD_CODE(x)    (((x) & 0xff) << 16)
 #define SPI_INSN_PAD_CODE(x)    (((x) & 0xff) << 24)
 #define SPI_TXFIFO_FULL  (1 << 31)
 #define SPI_RXFIFO_EMPTY (1 << 31)
 /* Values */
 #define SPI_CSMODE_AUTO         0
 #define SPI_CSMODE_HOLD         2
 #define SPI_CSMODE_OFF          3
 #define SPI_DIR_RX              0
 #define SPI_DIR_TX              1
 #define SPI_PROTO_S             0
 #define SPI_PROTO_D             1
 #define SPI_PROTO_Q             2
 #define SPI_ENDIAN_MSB          0
 #define SPI_ENDIAN_LSB          1
 #endif /* _SIFIVE_SPI_H */
--- a/bootrom/sdboot/include/devices/uart.h
+++ b/bootrom/sdboot/include/devices/uart.h
@ -0,0 +1,28 @@
 // See LICENSE for license details.
 #ifndef _SIFIVE_UART_H
 #define _SIFIVE_UART_H
 /* Register offsets */
 #define UART_REG_TXFIFO         0x00
 #define UART_REG_RXFIFO         0x04
 #define UART_REG_TXCTRL         0x08
 #define UART_REG_RXCTRL         0x0c
 #define UART_REG_IE             0x10
 #define UART_REG_IP             0x14
 #define UART_REG_DIV            0x18
 /* TXCTRL register */
 #define UART_TXEN               0x1
 #define UART_TXNSTOP            0x2
 #define UART_TXWM(x)            (((x) & 0xffff) << 16)
 /* RXCTRL register */
 #define UART_RXEN               0x1
 #define UART_RXWM(x)            (((x) & 0xffff) << 16)
 /* IP register */
 #define UART_IP_TXWM            0x1
 #define UART_IP_RXWM            0x2
 #endif /* _SIFIVE_UART_H */
--- a/bootrom/sdboot/include/platform.h
+++ b/bootrom/sdboot/include/platform.h
@ -0,0 +1,99 @@
 // See LICENSE for license details.
 #ifndef _SIFIVE_PLATFORM_H
 #define _SIFIVE_PLATFORM_H
 #include "const.h"
 #include "riscv_test_defaults.h"
 #include "devices/clint.h"
 #include "devices/gpio.h"
 #include "devices/plic.h"
 #include "devices/spi.h"
 #include "devices/uart.h"
 // Some things missing from the official encoding.h
 #if __riscv_xlen == 32
  #define MCAUSE_INT         0x80000000UL
  #define MCAUSE_CAUSE       0x7FFFFFFFUL
 #else
   #define MCAUSE_INT         0x8000000000000000UL
   #define MCAUSE_CAUSE       0x7FFFFFFFFFFFFFFFUL
 #endif
 /****************************************************************************
 * Platform definitions
 *****************************************************************************/
 // CPU info
 #define NUM_CORES 1
 #define GLOBAL_INT_SIZE 15
 #define GLOBAL_INT_MAX_PRIORITY 7
 // Memory map
 #define AXI_PCIE_HOST_1_00_A_CTRL_ADDR _AC(0x50000000,UL)
 #define AXI_PCIE_HOST_1_00_A_CTRL_SIZE _AC(0x4000000,UL)
 #define CLINT_CTRL_ADDR _AC(0x2000000,UL)
 #define CLINT_CTRL_SIZE _AC(0x10000,UL)
 #define DEBUG_CTRL_ADDR _AC(0x0,UL)
 #define DEBUG_CTRL_SIZE _AC(0x1000,UL)
 #define ERROR_MEM_ADDR _AC(0x3000,UL)
 #define ERROR_MEM_SIZE _AC(0x1000,UL)
 #define GPIO_CTRL_ADDR _AC(0x54002000,UL)
 #define GPIO_CTRL_SIZE _AC(0x1000,UL)
 #define MASKROM_MEM_ADDR _AC(0x10000,UL)
 #define MASKROM_MEM_SIZE _AC(0x2000,UL)
 #define MEMORY_MEM_ADDR _AC(0x80000000,UL)
 #define MEMORY_MEM_SIZE _AC(0x40000000,UL)
 #define PLIC_CTRL_ADDR _AC(0xc000000,UL)
 #define PLIC_CTRL_SIZE _AC(0x4000000,UL)
 #define SPI_CTRL_ADDR _AC(0x54001000,UL)
 #define SPI_CTRL_SIZE _AC(0x1000,UL)
 #define TEST_CTRL_ADDR _AC(0x4000,UL)
 #define TEST_CTRL_SIZE _AC(0x1000,UL)
 #define UART_CTRL_ADDR _AC(0x54000000,UL)
 #define UART_CTRL_SIZE _AC(0x1000,UL)
 // IOF masks
 // Interrupt numbers
 #define UART_INT_BASE 1
 #define SPI_INT_BASE 2
 #define GPIO_INT_BASE 3
 #define AXI_PCIE_HOST_1_00_A_INT_BASE 7
 // Helper functions
 #define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
 #define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
 #define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
 // Bulk set bits in `reg` to either 0 or 1.
 // E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
 // E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
 #define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
 #define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
 #define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
 #define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset)
 #define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset)
 #define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
 #define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset)
 #define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset)
 #define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
 #define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset)
 #define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset)
 #define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset)
 #define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
 #define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
 #define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset)
 #define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset)
 #define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
 #define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset)
 #define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset)
 #define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
 #define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset)
 #define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset)
 #define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset)
 // Misc
 #endif /* _SIFIVE_PLATFORM_H */
--- a/bootrom/sdboot/include/riscv_test_defaults.h
+++ b/bootrom/sdboot/include/riscv_test_defaults.h
@ -0,0 +1,81 @@
 // See LICENSE for license details.
 #ifndef _RISCV_TEST_DEFAULTS_H
 #define _RISCV_TEST_DEFAULTS_H
 #define TESTNUM x28
 #define TESTBASE 0x4000
 #define RVTEST_RV32U \
  .macro init; \
  .endm
 #define RVTEST_RV64U \
  .macro init; \
  .endm
 #define RVTEST_RV32UF \
  .macro init; \
  /* If FPU exists, initialize FCSR. */ \
  csrr t0, misa; \
  andi t0, t0, 1 << ('F' - 'A'); \
  beqz t0, 1f; \
  /* Enable FPU if it exists. */ \
  li t0, MSTATUS_FS; \
  csrs mstatus, t0; \
  fssr x0; \
 1: ; \
  .endm
 #define RVTEST_RV64UF \
  .macro init; \
  /* If FPU exists, initialize FCSR. */ \
  csrr t0, misa; \
  andi t0, t0, 1 << ('F' - 'A'); \
  beqz t0, 1f; \
  /* Enable FPU if it exists. */ \
  li t0, MSTATUS_FS; \
  csrs mstatus, t0; \
  fssr x0; \
 1: ; \
  .endm
 #define RVTEST_CODE_BEGIN \
  .section .text.init; \
  .globl _prog_start; \
 _prog_start: \
  init;
 #define RVTEST_CODE_END \
  unimp
 #define RVTEST_PASS \
  fence; \
  li t0, TESTBASE; \
  li t1, 0x5555; \
  sw t1, 0(t0); \
 1: \
  j 1b;
 #define RVTEST_FAIL \
  li t0, TESTBASE; \
  li t1, 0x3333; \
  slli a0, a0, 16; \
  add a0, a0, t1; \
  sw a0, 0(t0); \
 1: \
  j 1b;
 #define EXTRA_DATA
 #define RVTEST_DATA_BEGIN \
  EXTRA_DATA \
  .align 4; .global begin_signature; begin_signature:
 #define RVTEST_DATA_END \
  _msg_init: .asciz "RUN\r\n"; \
  _msg_pass: .asciz "PASS"; \
  _msg_fail: .asciz "FAIL "; \
  _msg_end: .asciz "\r\n"; \
  .align 4; .global end_signature; end_signature:
 #endif /* _RISCV_TEST_DEFAULTS_H */
--- a/bootrom/sdboot/include/sections.h
+++ b/bootrom/sdboot/include/sections.h
@ -0,0 +1,17 @@
 // See LICENSE for license details.
 #ifndef _SECTIONS_H
 #define _SECTIONS_H
 extern unsigned char _rom[];
 extern unsigned char _rom_end[];
 extern unsigned char _ram[];
 extern unsigned char _ram_end[];
 extern unsigned char _ftext[];
 extern unsigned char _etext[];
 extern unsigned char _fbss[];
 extern unsigned char _ebss[];
 extern unsigned char _end[];
 #endif /* _SECTIONS_H */
--- a/bootrom/sdboot/kprintf.c
+++ b/bootrom/sdboot/kprintf.c
@ -0,0 +1,75 @@
 // See LICENSE for license details.
 #include <stdarg.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include "kprintf.h"
 static inline void _kputs(const char *s)
 {
 	char c;
 	for (; (c = *s) != '\0'; s++)
 		kputc(c);
 }
 void kputs(const char *s)
 {
 	_kputs(s);
 	kputc('\r');
 	kputc('\n');
 }
 void kprintf(const char *fmt, ...)
 {
 	va_list vl;
 	bool is_format, is_long, is_char;
 	char c;
 	va_start(vl, fmt);
 	is_format = false;
 	is_long = false;
 	is_char = false;
 	while ((c = *fmt++) != '\0') {
 		if (is_format) {
 			switch (c) {
 			case 'l':
 				is_long = true;
 				continue;
 			case 'h':
 				is_char = true;
 				continue;
 			case 'x': {
 				unsigned long n;
 				long i;
 				if (is_long) {
 					n = va_arg(vl, unsigned long);
 					i = (sizeof(unsigned long) << 3) - 4;
 				} else {
 					n = va_arg(vl, unsigned int);
 					i = is_char ? 4 : (sizeof(unsigned int) << 3) - 4;
 				}
 				for (; i >= 0; i -= 4) {
 					long d;
 					d = (n >> i) & 0xF;
 					kputc(d < 10 ? '0' + d : 'a' + d - 10);
 				}
 				break;
 			}
 			case 's':
 				_kputs(va_arg(vl, const char *));
 				break;
 			case 'c':
 				kputc(va_arg(vl, int));
 				break;
 			}
 			is_format = false;
 			is_long = false;
 			is_char = false;
 		} else if (c == '%') {
 			is_format = true;
 		} else {
 			kputc(c);
 		}
 	}
 	va_end(vl);
 }
--- a/bootrom/sdboot/kprintf.h
+++ b/bootrom/sdboot/kprintf.h
@ -0,0 +1,49 @@
 // See LICENSE for license details.
 #ifndef _SDBOOT_KPRINTF_H
 #define _SDBOOT_KPRINTF_H
 #include <platform.h>
 #include <stdint.h>
 #define REG32(p, i)	((p)[(i) >> 2])
 #ifndef UART_CTRL_ADDR
  #ifndef UART_NUM
    #define UART_NUM 0
  #endif
  #define _CONCAT3(A, B, C) A ## B ## C
  #define _UART_CTRL_ADDR(UART_NUM) _CONCAT3(UART, UART_NUM, _CTRL_ADDR)
  #define UART_CTRL_ADDR _UART_CTRL_ADDR(UART_NUM)
 #endif
 static volatile uint32_t * const uart = (void *)(UART_CTRL_ADDR);
 static inline void kputc(char c)
 {
 	volatile uint32_t *tx = &REG32(uart, UART_REG_TXFIFO);
 #ifdef __riscv_atomic
 	int32_t r;
 	do {
 		__asm__ __volatile__ (
 			"amoor.w %0, %2, %1\n"
 			: "=r" (r), "+A" (*tx)
 			: "r" (c));
 	} while (r < 0);
 #else
 	while ((int32_t)(*tx) < 0);
 	*tx = c;
 #endif
 }
 extern void kputs(const char *);
 extern void kprintf(const char *, ...);
 #ifdef DEBUG
 #define dprintf(s, ...)	kprintf((s), ##__VA_ARGS__)
 #define dputs(s)	kputs((s))
 #else
 #define dprintf(s, ...) do { } while (0)
 #define dputs(s)	do { } while (0)
 #endif
 #endif /* _SDBOOT_KPRINTF_H */
--- a/bootrom/sdboot/linker/memory.lds
+++ b/bootrom/sdboot/linker/memory.lds
@ -0,0 +1,14 @@
 MEMORY
 {
  debug_ctrl (rwx) : ORIGIN = 0x0, LENGTH = 0x1000
  error_mem (rw) : ORIGIN = 0x3000, LENGTH = 0x1000
  test_ctrl (rw) : ORIGIN = 0x4000, LENGTH = 0x1000
  maskrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x2000
  clint_ctrl (rw) : ORIGIN = 0x2000000, LENGTH = 0x10000
  plic_ctrl (rw) : ORIGIN = 0xc000000, LENGTH = 0x4000000
  axi_pcie_host_1_00_a_ctrl (rw) : ORIGIN = 0x50000000, LENGTH = 0x4000000
  uart_ctrl (rw) : ORIGIN = 0x54000000, LENGTH = 0x1000
  spi_ctrl (rw) : ORIGIN = 0x54001000, LENGTH = 0x1000
  gpio_ctrl (rw) : ORIGIN = 0x54002000, LENGTH = 0x1000
  memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000
 }
--- a/bootrom/sdboot/linker/sdboot.elf.lds
+++ b/bootrom/sdboot/linker/sdboot.elf.lds
@ -0,0 +1,79 @@
 OUTPUT_ARCH("riscv")
 ENTRY(_prog_start)
 INCLUDE memory.lds
 PHDRS
 {
  text PT_LOAD;
  data PT_LOAD;
  bss PT_LOAD;
 }
 SECTIONS
 {
  PROVIDE(_ram = ORIGIN(memory_mem));
  PROVIDE(_ram_end = _ram + LENGTH(memory_mem));
  .text ALIGN((ORIGIN(maskrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(maskrom_mem) + 0x0), 8)) {
    PROVIDE(_ftext = .);
    *(.text.init)
    *(.text.unlikely .text.unlikely.*)
    *(.text .text.* .gnu.linkonce.t.*)
    PROVIDE(_etext = .);
    . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */
  } >maskrom_mem  :text
  .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) {
    *(.eh_frame)
  } >maskrom_mem  :text
  .rodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT {
    *(.rodata .rodata.* .gnu.linkonce.r.*)
  } >maskrom_mem  :data
  .srodata ALIGN((ADDR(.rodata) + SIZEOF(.rodata)), 8) : AT(ALIGN((LOADADDR(.rodata) + SIZEOF(.rodata)), 8)) ALIGN_WITH_INPUT {
    *(.srodata.cst16)
    *(.srodata.cst8)
    *(.srodata.cst4)
    *(.srodata.cst2)
    *(.srodata.*)
  } >maskrom_mem  :data
  .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT {
    *(.data .data.* .gnu.linkonce.d.*)
    *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */
  } >maskrom_mem  :data
  .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT {
    *(.sdata .sdata.* .gnu.linkonce.s.*)
  } >maskrom_mem  :data
  PROVIDE(_data = ADDR(.rodata));
  PROVIDE(_data_lma = LOADADDR(.rodata));
  PROVIDE(_edata = .);
  .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) {
    PROVIDE(_fbss = .);
    PROVIDE(__global_pointer$ = . + 0x7C0);
    *(.sbss .sbss.* .gnu.linkonce.sb.*)
    *(.bss .bss.* .gnu.linkonce.b.*)
    . = ALIGN(8);
    PROVIDE(_ebss = .);
  } >memory_mem  :bss
  PROVIDE(_end = .);
  /*
   * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem))
   * heap_stack_min_size: 4096
   * heap_stack_max_size: 1048576
   */
  PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8));
  PROVIDE(_heap_end = _sp - 2048);
  /* This section is a noop and is only used for the ASSERT */
  .stack : {
    ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack");
  }
 }
--- a/bootrom/sdboot/sd.c
+++ b/bootrom/sdboot/sd.c
@ -0,0 +1,225 @@
 // See LICENSE for license details.
 #include <stdint.h>
 #include <platform.h>
 #include "common.h"
 #define DEBUG
 #include "kprintf.h"
 #define MAX_CORES 8
 #define PAYLOAD_SIZE	(16 << 11)
 #define F_CLK 50000000UL
 static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
 static inline uint8_t spi_xfer(uint8_t d)
 {
 	int32_t r;
 	REG32(spi, SPI_REG_TXFIFO) = d;
 	do {
 		r = REG32(spi, SPI_REG_RXFIFO);
 	} while (r < 0);
 	return r;
 }
 static inline uint8_t sd_dummy(void)
 {
 	return spi_xfer(0xFF);
 }
 static uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc)
 {
 	unsigned long n;
 	uint8_t r;
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_HOLD;
 	sd_dummy();
 	spi_xfer(cmd);
 	spi_xfer(arg >> 24);
 	spi_xfer(arg >> 16);
 	spi_xfer(arg >> 8);
 	spi_xfer(arg);
 	spi_xfer(crc);
 	n = 1000;
 	do {
 		r = sd_dummy();
 		if (!(r & 0x80)) {
 //			dprintf("sd:cmd: %hx\r\n", r);
 			goto done;
 		}
 	} while (--n > 0);
 	kputs("sd_cmd: timeout");
 done:
 	return r;
 }
 static inline void sd_cmd_end(void)
 {
 	sd_dummy();
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
 }
 static void sd_poweron(void)
 {
 	long i;
 	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
 	for (i = 10; i > 0; i--) {
 		sd_dummy();
 	}
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_AUTO;
 }
 static int sd_cmd0(void)
 {
 	int rc;
 	dputs("CMD0");
 	rc = (sd_cmd(0x40, 0, 0x95) != 0x01);
 	sd_cmd_end();
 	return rc;
 }
 static int sd_cmd8(void)
 {
 	int rc;
 	dputs("CMD8");
 	rc = (sd_cmd(0x48, 0x000001AA, 0x87) != 0x01);
 	sd_dummy(); /* command version; reserved */
 	sd_dummy(); /* reserved */
 	rc |= ((sd_dummy() & 0xF) != 0x1); /* voltage */
 	rc |= (sd_dummy() != 0xAA); /* check pattern */
 	sd_cmd_end();
 	return rc;
 }
 static void sd_cmd55(void)
 {
 	sd_cmd(0x77, 0, 0x65);
 	sd_cmd_end();
 }
 static int sd_acmd41(void)
 {
 	uint8_t r;
 	dputs("ACMD41");
 	do {
 		sd_cmd55();
 		r = sd_cmd(0x69, 0x40000000, 0x77); /* HCS = 1 */
 	} while (r == 0x01);
 	return (r != 0x00);
 }
 static int sd_cmd58(void)
 {
 	int rc;
 	dputs("CMD58");
 	rc = (sd_cmd(0x7A, 0, 0xFD) != 0x00);
 	rc |= ((sd_dummy() & 0x80) != 0x80); /* Power up status */
 	sd_dummy();
 	sd_dummy();
 	sd_dummy();
 	sd_cmd_end();
 	return rc;
 }
 static int sd_cmd16(void)
 {
 	int rc;
 	dputs("CMD16");
 	rc = (sd_cmd(0x50, 0x200, 0x15) != 0x00);
 	sd_cmd_end();
 	return rc;
 }
 static uint16_t crc16_round(uint16_t crc, uint8_t data) {
 	crc = (uint8_t)(crc >> 8) | (crc << 8);
 	crc ^= data;
 	crc ^= (uint8_t)(crc >> 4) & 0xf;
 	crc ^= crc << 12;
 	crc ^= (crc & 0xff) << 5;
 	return crc;
 }
 #define SPIN_SHIFT	6
 #define SPIN_UPDATE(i)	(!((i) & ((1 << SPIN_SHIFT)-1)))
 #define SPIN_INDEX(i)	(((i) >> SPIN_SHIFT) & 0x3)
 static const char spinner[] = { '-', '/', '|', '\\' };
 static int copy(void)
 {
 	volatile uint8_t *p = (void *)(PAYLOAD_DEST);
 	long i = PAYLOAD_SIZE;
 	int rc = 0;
 	dputs("CMD18");
 	kprintf("LOADING  ");
 	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 20000000UL);
 	if (sd_cmd(0x52, 0, 0xE1) != 0x00) {
 		sd_cmd_end();
 		return 1;
 	}
 	do {
 		uint16_t crc, crc_exp;
 		long n;
 		crc = 0;
 		n = 512;
 		while (sd_dummy() != 0xFE);
 		do {
 			uint8_t x = sd_dummy();
 			*p++ = x;
 			crc = crc16_round(crc, x);
 		} while (--n > 0);
 		crc_exp = ((uint16_t)sd_dummy() << 8);
 		crc_exp |= sd_dummy();
 		if (crc != crc_exp) {
 			kputs("\b- CRC mismatch ");
 			rc = 1;
 			break;
 		}
 		if (SPIN_UPDATE(i)) {
 			kputc('\b');
 			kputc(spinner[SPIN_INDEX(i)]);
 		}
 	} while (--i > 0);
 	sd_cmd_end();
 	sd_cmd(0x4C, 0, 0x01);
 	sd_cmd_end();
 	kputs("\b ");
 	return rc;
 }
 int main(void)
 {
 	REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
 	kputs("INIT");
 	sd_poweron();
 	if (sd_cmd0() ||
 	    sd_cmd8() ||
 	    sd_acmd41() ||
 	    sd_cmd58() ||
 	    sd_cmd16() ||
 	    copy()) {
 		kputs("ERROR");
 		return 1;
 	}
 	kputs("BOOT");
 	__asm__ __volatile__ ("fence.i" : : : "memory");
 	return 0;
 }
--- a/bootrom/u500vc707devkit.img
+++ b/bootrom/u500vc707devkit.img
--- a/bootrom/xip/Makefile
+++ b/bootrom/xip/Makefile
@ -0,0 +1,45 @@
 # RISCV environment variable must be set
 CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
 OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
 CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
 LFLAGS=-static -nostdlib
 dtb := $(BUILD_DIR)/$(CONFIG).dtb
 $(dtb): $(BUILD_DIR)/$(CONFIG).dts
 	dtc -I dts -O dtb -o $@ $<
 .PHONY: dtb
 dtb: $(dtb)
 elf := $(BUILD_DIR)/xip.elf
 $(elf): xip.S $(dtb)
 	$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
 .PHONY: elf
 elf: $(elf)
 bin := $(BUILD_DIR)/xip.bin
 $(bin): $(elf)
 	$(OBJCOPY) -O binary $< $@
 .PHONY: bin
 bin: $(bin)
 hex := $(BUILD_DIR)/xip.hex
 $(hex): $(bin)
 	od -t x4 -An -w4 -v $< > $@
 .PHONY: hex
 hex: $(hex)
 romgen := $(BUILD_DIR)/rom.v
 $(romgen): $(hex)
 	$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
 .PHONY: romgen
 romgen: $(romgen)
 .PHONY: clean
 clean::
 	rm -rf $(hex) $(elf) 
--- a/bootrom/xip/xip.S
+++ b/bootrom/xip/xip.S
@ -2,25 +2,15 @@
 // Execute in place
 // Jump directly to XIP_TARGET_ADDR
-  .text
+  .section .text.init
  .option norvc
  .globl _start
 _start:
-  j 1f
+  csrr a0, mhartid
-  nop
+  la a1, dtb
  nop
 #ifdef CONFIG_STRING
  .word cfg_string
 #else
  .word 0  // Filled in by GenerateBootROM in Chisel
 #endif
 1:
  li t0, XIP_TARGET_ADDR
  jr t0
  .section .rodata
-#ifdef CONFIG_STRING
+dtb:
-cfg_string:
+  .incbin DEVICE_TREE
  .incbin CONFIG_STRING
 #endif
--- a/build.sbt
+++ b/build.sbt
@ -25,6 +25,10 @@ lazy val sifiveBlocks = (project in file("sifive-blocks")).
  dependsOn(rocketChip).
  settings(commonSettings: _*)
-lazy val freedomPlatforms = (project in file(".")).
+lazy val fpgaShells = (project in file("fpga-shells")).
  dependsOn(rocketChip, sifiveBlocks).
  settings(commonSettings: _*)
 lazy val freedomPlatforms = (project in file(".")).
  dependsOn(rocketChip, sifiveBlocks, fpgaShells).
  settings(commonSettings: _*)
--- a/common.mk
+++ b/common.mk
@ -11,11 +11,23 @@
 # Optional variables:
 # - EXTRA_FPGA_VSRCS
 # export to bootloader
 export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
 # export to fpga-shells
 export FPGA_TOP_SYSTEM=$(MODEL)
 export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
 export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
 export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
 export BUILD_DIR
 EXTRA_FPGA_VSRCS ?=
 PATCHVERILOG ?= ""
 BOOTROM_DIR ?= ""
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
-rocketchip_dir := $(base_dir)/rocket-chip
+export rocketchip_dir := $(base_dir)/rocket-chip
 SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
 # Build firrtl.jar and put it where chisel3 can find it.
@ -25,6 +37,8 @@ FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Drive
 $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
 	$(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
 	touch $(FIRRTL_JAR)
 	mkdir -p $(rocketchip_dir)/lib
 	cp -p $(FIRRTL_JAR) rocket-chip/lib
 	mkdir -p $(rocketchip_dir)/chisel3/lib
 	cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
@ -32,7 +46,7 @@ $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.sc
 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
 $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(SBT) "run-main rocketchip.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
+	$(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
 .PHONY: firrtl
 firrtl: $(firrtl)
@ -45,15 +59,24 @@ ifneq ($(PATCHVERILOG),"")
 	$(PATCHVERILOG)
 endif
 .PHONY: verilog
 verilog: $(verilog)
 romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
 $(romgen): $(verilog)
 ifneq ($(BOOTROM_DIR),"")
 	$(MAKE) -C $(BOOTROM_DIR) romgen
 	mv $(BUILD_DIR)/rom.v $@
 endif
 .PHONY: romgen
 romgen: $(romgen)
 # Build .mcs
 mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(verilog)
+$(mcs): $(romgen)
-	VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
+	VSRCS="$(VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
-	cp $(FPGA_DIR)/obj/system.mcs $@
+	cp $(BUILD_DIR)/$(MODEL)/obj/system.mcs $@
 .PHONY: mcs
 mcs: $(mcs)
@ -61,5 +84,8 @@ mcs: $(mcs)
 # Clean
 .PHONY: clean
 clean:
 ifneq ($(BOOTROM_DIR),"")
 	$(MAKE) -C $(BOOTROM_DIR) clean
 endif
 	$(MAKE) -C $(FPGA_DIR) clean
 	rm -rf $(BUILD_DIR)
--- a/1
+++ b/1
@ -0,0 +1 @@
 Subproject commit 2389e6e95717caca782e7444422da16fef687188
--- a/fpga/e300artydevkit/.gitignore
+++ b/fpga/e300artydevkit/.gitignore
@ -1,8 +0,0 @@
 .Xil
 .ip_user_files
 *.log
 *.html
 *.xml
 fsm_encoding.os
 obj
 src/generated
--- a/fpga/e300artydevkit/Makefile
+++ b/fpga/e300artydevkit/Makefile
@ -1,27 +0,0 @@
 VIVADO ?= vivado
 VIVADOFLAGS := \
 	-nojournal -mode batch \
 	-source script/board.tcl \
 	-source script/prologue.tcl
 # Path to a program in raw binary format to be flashed into the address that the
 # bootrom jumps to.
 FLASHED_PROGRAM ?=
 bit := obj/system.bit
 $(bit): script/impl.tcl  script/init.tcl
 	VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
 .PHONY: bit
 bit: $(bit)
 mcs := obj/system.mcs
 $(mcs): $(bit)
 	$(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^ $(FLASHED_PROGRAM)
 .PHONY: mcs
 mcs: $(mcs)
 .PHONY: clean
 clean::
 	rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log
--- a/fpga/e300artydevkit/constrs/arty-config.xdc
+++ b/fpga/e300artydevkit/constrs/arty-config.xdc
@ -1,5 +0,0 @@
 set_property -dict [list \
  CONFIG_VOLTAGE {3.3} \
  CFGBVS {VCCO} \
  BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \
  ] [current_design]
--- a/fpga/e300artydevkit/constrs/arty-master.xdc
+++ b/fpga/e300artydevkit/constrs/arty-master.xdc
@ -1,230 +0,0 @@
 ## This file is a general .xdc for the ARTY Rev. B
 ## To use it in a project:
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
 ## Clock signal
 set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
 ##Switches
 set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw_0 }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
 set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw_1 }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
 set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw_2 }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
 set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw_3 }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
 ##RGB LEDs
 set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
 set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
 set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
 set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
 set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
 set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
 set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
 set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
 set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
 #set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
 #set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
 #set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
 ##LEDs
 set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { led_0 }]; #IO_L24N_T3_35 Sch=led[4]
 set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { led_1 }]; #IO_25_35 Sch=led[5]
 set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { led_2 }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
 set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { led_3 }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
 ##Buttons
 set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn_0 }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
 set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn_1 }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
 set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn_2 }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
 set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn_3 }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
 ##Pmod Header JA
 set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja_0 }]; #IO_0_15 Sch=ja[1]
 set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { ja_1 }]; #IO_L4P_T0_15 Sch=ja[2]
 #set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { ja_2 }]; #IO_L4N_T0_15 Sch=ja[3]
 #set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { ja_3 }]; #IO_L6P_T0_15 Sch=ja[4]
 #set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { ja_4 }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
 #set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { ja_5 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
 #set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ja_6 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
 #set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja_7 }]; #IO_25_15 Sch=ja[10]
 ##Pmod Header JB
 #set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb_0 }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
 #set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb_1 }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
 #set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb_2 }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
 #set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb_3 }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
 #set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb_4 }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
 #set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb_5 }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
 #set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb_6 }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
 #set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { jb_7 }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
 ##Pmod Header JC
 #set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
 #set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
 #set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
 #set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
 #set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
 #set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
 #set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
 #set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
 ##Pmod Header JD
 set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { jd_0 }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
 set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { jd_1 }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
 set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { jd_2 }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
 #set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { jd_3 }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
 set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { jd_4 }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
 set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { jd_5 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
 set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { jd_6 }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
 #set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { jd_7 }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
 ##USB-UART Interface (FTDI FT2232H)
 set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33  } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
 set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33  } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
 ##ChipKit Single Ended Analog Inputs
 ##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
 ##      These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
 #set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]
 #set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0]
 #set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1]
 #set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1]
 #set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2]
 #set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2]
 #set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3]
 #set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3]
 #set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4]
 #set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4]
 #set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5]
 #set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5]
 ##ChipKit Digital I/O Low
 set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
 set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
 set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
 set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
 set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
 set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
 set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
 set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
 set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
 set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
 set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
 set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
 set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
 set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
 ##ChipKit Digital I/O On Outer Analog Header
 ##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19)
 set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0]
 set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1]
 set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2]
 set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3]
 set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
 set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
 ##ChipKit Digital I/O On Inner Analog Header
 ##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11)
 #set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
 #set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
 #set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
 #set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
 #set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
 #set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
 ##ChipKit Digital I/O High
 #set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
 #set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
 #set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
 #set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_25_14 Sch=ck_io[29]
 #set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_0_14 Sch=ck_io[30]
 #set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
 #set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
 #set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
 #set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
 #set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
 #set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
 #set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
 #set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
 #set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
 #set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
 #set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
 ## ChipKit SPI
 set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
 set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
 set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
 set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
 ## ChipKit I2C
 #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
 #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
 #set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
 #set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
 ##Misc. ChipKit signals
 #set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
 set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
 ##SMSC Ethernet PHY
 #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
 #set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
 #set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
 #set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
 #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
 #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
 #set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
 #set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
 #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
 #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
 #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
 #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
 #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
 #set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
 #set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
 #set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
 #set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
 #set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
 #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
 ##Quad SPI Flash
 set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33  IOB TRUE } [get_ports { qspi_sck }];
 create_clock -add -name qspi_sck_pin -period 20.00 -waveform {0 10}    [get_ports { qspi_sck }];
 set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33  IOB TRUE } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
 set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33  IOB TRUE  PULLUP TRUE } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
 set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33  IOB TRUE  PULLUP TRUE } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
 set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33  IOB TRUE  PULLUP TRUE } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
 set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33  IOB TRUE  PULLUP TRUE } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
 ##Power Measurements
 #set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
 #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
 #set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
 #set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
 #set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
 #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
 #set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
 #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
--- a/fpga/e300artydevkit/script/board.tcl
+++ b/fpga/e300artydevkit/script/board.tcl
@ -1,4 +0,0 @@
 set name {arty_e300devkit}
 set part_fpga {xc7a35ticsg324-1L}
 set part_board {digilentinc.com:arty:part0:1.1}
 set bootrom_inst {rom}
--- a/fpga/e300artydevkit/script/cfgmem.tcl
+++ b/fpga/e300artydevkit/script/cfgmem.tcl
@ -1,10 +0,0 @@
 lassign $argv mcsfile bitfile datafile
 set iface spix4
 set size 16
 set bitaddr 0x0
 write_cfgmem -format mcs -interface $iface -size $size \
  -loadbit "up ${bitaddr} ${bitfile}" \
  -loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
  -file $mcsfile -force
--- a/fpga/e300artydevkit/script/impl.tcl
+++ b/fpga/e300artydevkit/script/impl.tcl
@ -1,53 +0,0 @@
 set_param {messaging.defaultLimit} 1000000
 read_ip [glob -directory $ipdir [file join * {*.xci}]]
 synth_design -top $top -flatten_hierarchy rebuilt
 write_checkpoint -force [file join $wrkdir post_synth]
 opt_design
 write_checkpoint -force [file join $wrkdir post_opt]
 place_design
 write_checkpoint -force [file join $wrkdir post_place]
 phys_opt_design
 power_opt_design
 route_design
 write_checkpoint -force [file join $wrkdir post_route]
 write_bitstream -force [file join $wrkdir "${top}.bit"]
 write_sdf -force [file join $wrkdir "${top}.sdf"]
 write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
 write_debug_probes -force [file join $wrkdir "${top}.ltx"]
 # AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
 # Work around the write_mem_info command not supporting "processor-less"
 # (non-Microblaze) designs.
 set bram_inst [get_cells -hierarchical "bram"]
 if {$bram_inst ne ""} {
  source [file join $scriptdir "bram.tcl"]
  write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
 }
 if {[info exists bootrom_inst]} {
  puts "Generating bootrom.mmi ..."
  set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
  if {$rom_inst ne ""} {
    source [file join $scriptdir "bram.tcl"]
    write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
  }
 }
 set rptdir [file join $wrkdir report]
 file mkdir $rptdir
 set rptutil [file join $rptdir utilization.txt]
 report_datasheet -file [file join $rptdir datasheet.txt]
 report_utilization -hierarchical -file $rptutil
 report_clock_utilization -file $rptutil -append
 report_ram_utilization -file $rptutil -append -detail
 report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
 report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
 report_drc -file [file join $rptdir drc.txt]
 report_io -file [file join $rptdir io.txt]
 report_clocks -file [file join $rptdir clocks.txt]
--- a/fpga/e300artydevkit/script/init.tcl
+++ b/fpga/e300artydevkit/script/init.tcl
@ -1,41 +0,0 @@
 proc recglob { basedir pattern } {
  set dirlist [glob -nocomplain -directory $basedir -type d *]
  set findlist [glob -nocomplain -directory $basedir $pattern]
  foreach dir $dirlist {
    set reclist [recglob $dir $pattern]
    set findlist [concat $findlist $reclist]
  }
  return $findlist
 }
 proc findincludedir { basedir pattern } {
  #find all subdirectories containing ".vh" files
  set vhfiles [recglob $basedir $pattern]
  set vhdirs {}
  foreach match $vhfiles {
    lappend vhdirs [file dir $match]
  }
  set uniquevhdirs [lsort -unique $vhdirs]
  return $uniquevhdirs
 }
 file mkdir $ipdir
 update_ip_catalog -rebuild
 source [file join $scriptdir ip.tcl]
 # AR 58526 <http://www.xilinx.com/support/answers/58526.html>
 set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
 set obj [get_ips]
 generate_target all $obj
 export_ip_user_files -of_objects $obj -no_script -force
 set obj [current_fileset]
 # Xilinx bug workaround
 # scrape IP tree for directories containing .vh files
 # [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
 set property_include_dirs [get_property include_dirs $obj]
 set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
 set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
 set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
--- a/fpga/e300artydevkit/script/ip.tcl
+++ b/fpga/e300artydevkit/script/ip.tcl
@ -1,19 +0,0 @@
 create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force
 set_property -dict [list \
  CONFIG.PRIMITIVE {MMCM} \
  CONFIG.RESET_TYPE {ACTIVE_LOW} \
  CONFIG.CLKOUT1_USED {true} \
  CONFIG.CLKOUT2_USED {true} \
  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \
  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \
  ] [get_ips mmcm]
 create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force
 set_property -dict [list \
  CONFIG.C_EXT_RESET_HIGH {false} \
  CONFIG.C_AUX_RESET_HIGH {false} \
  CONFIG.C_NUM_BUS_RST {1} \
  CONFIG.C_NUM_PERP_RST {1} \
  CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
  CONFIG.C_NUM_PERP_ARESETN {1} \
  ] [get_ips reset_sys]
--- a/fpga/e300artydevkit/script/prologue.tcl
+++ b/fpga/e300artydevkit/script/prologue.tcl
@ -1,69 +0,0 @@
 set scriptdir [file dirname [info script]]
 set commondir [file dirname $scriptdir]
 set srcdir [file join $commondir src]
 set constrsdir [file join $commondir constrs]
 set wrkdir [file join [pwd] obj]
 set ipdir [file join $wrkdir ip]
 set top {system}
 create_project -part $part_fpga -in_memory
 set_property -dict [list \
  BOARD_PART $part_board \
  TARGET_LANGUAGE {Verilog} \
  SIMULATOR_LANGUAGE {Mixed} \
  TARGET_SIMULATOR {XSim} \
  DEFAULT_LIB {xil_defaultlib} \
  IP_REPO_PATHS $ipdir \
  ] [current_project]
 proc recglob { basedir pattern } {
  set dirlist [glob -nocomplain -directory $basedir -type d *]
  set findlist [glob -nocomplain -directory $basedir $pattern]
  foreach dir $dirlist {
    set reclist [recglob $dir $pattern]
    set findlist [concat $findlist $reclist]
  }
  return $findlist
 }
 if {[get_filesets -quiet sources_1] eq ""} {
  create_fileset -srcset sources_1
 }
 set obj [current_fileset]
 set srcmainverilogfiles [recglob $srcdir "*.v"]
 add_files -norecurse -fileset $obj $srcmainverilogfiles
 if {[info exists ::env(EXTRA_VSRCS)]} {
  set extra_vsrcs [split $::env(EXTRA_VSRCS)]
  foreach extra_vsrc $extra_vsrcs {
    add_files -norecurse -fileset $obj $extra_vsrc
  }
 }
 ## TODO: These paths and files should come from the caller, not within this script.
 #if {[file exists [file join $srcdir include verilog]]} {
 #  add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
 #  add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
 #}
 set vsrc_top $::env(VSRC_TOP)
 set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
 add_files -norecurse -fileset $obj $vsrc_top
 if {[get_filesets -quiet sim_1] eq ""} {
  create_fileset -simset sim_1
 }
 set obj [current_fileset -simset]
 add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
 set_property TOP {tb} $obj
 if {[get_filesets -quiet constrs_1] eq ""} {
  create_fileset -constrset constrs_1
 }
 set obj [current_fileset -constrset]
 add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
--- a/fpga/e300artydevkit/src/system.v
+++ b/fpga/e300artydevkit/src/system.v
--- a/fpga/u500vc707devkit/Makefile
+++ b/fpga/u500vc707devkit/Makefile
@ -1,23 +0,0 @@
 VIVADO ?= vivado
 VIVADOFLAGS := \
 	-nojournal -mode batch \
 	-source script/board.tcl \
 	-source script/prologue.tcl
 bit := obj/system.bit
 $(bit): script/impl.tcl  script/init.tcl
 	VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
 .PHONY: bit
 bit: $(bit)
 mcs := obj/system.mcs
 $(mcs): $(bit)
 	$(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^
 .PHONY: mcs
 mcs: $(mcs)
 .PHONY: clean
 clean::
 	rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log
--- a/fpga/u500vc707devkit/constrs/vc707-master.xdc
+++ b/fpga/u500vc707devkit/constrs/vc707-master.xdc
@ -1,90 +0,0 @@
 #---------------Physical Constraints-----------------
 set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p]
 set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n]
 set_property BOARD_PIN {reset} [get_ports reset]
 # The MIG has its own create_clock
 #create_clock -name ddr_ref_clk -period 5.0 [get_ports sys_diff_clock_clk_p]
 set_input_jitter [get_clocks -of_objects [get_ports sys_diff_clock_clk_p]] 0.5
 set_property BOARD_PIN {leds_8bits_tri_o_0} [get_ports led[0]]
 set_property BOARD_PIN {leds_8bits_tri_o_1} [get_ports led[1]]
 set_property BOARD_PIN {leds_8bits_tri_o_2} [get_ports led[2]]
 set_property BOARD_PIN {leds_8bits_tri_o_3} [get_ports led[3]]
 set_property BOARD_PIN {leds_8bits_tri_o_4} [get_ports led[4]]
 set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led[5]]
 set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led[6]]
 set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led[7]]
 set_property PACKAGE_PIN AU33 [get_ports uart_rx]
 set_property IOSTANDARD LVCMOS18 [get_ports uart_rx]
 set_property IOB TRUE [get_ports uart_rx]
 set_property PACKAGE_PIN AT32 [get_ports uart_ctsn]
 set_property IOSTANDARD LVCMOS18 [get_ports uart_ctsn]
 set_property IOB TRUE [get_ports uart_ctsn]
 set_property PACKAGE_PIN AU36 [get_ports uart_tx]
 set_property IOSTANDARD LVCMOS18 [get_ports uart_tx]
 set_property IOB TRUE [get_ports uart_tx]
 set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
 set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
 set_property IOB TRUE [get_ports uart_rtsn]
 set_property IOB TRUE [get_cells "top/uart0/txm/out_reg"]
 set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
 # PCI Express 
 #FMC 1 refclk
 #set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports {pci_exp_refclk_rxp}]
 set_property PACKAGE_PIN A10 [get_ports {pci_exp_refclk_rxp}]
 set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
 create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
 set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
 set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
 set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
 set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
 set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
 # JTAG
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
 set_property -dict { PACKAGE_PIN R32  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TCK}]
 set_property -dict { PACKAGE_PIN W36  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TMS}]
 set_property -dict { PACKAGE_PIN W37  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDI}]
 set_property -dict { PACKAGE_PIN V40  IOSTANDARD LVCMOS18  PULLUP TRUE } [get_ports {jtag_TDO}]
 # SDIO
 #set_property -dict { PACKAGE_PIN AR32  IOSTANDARD LVCMOS18 } [get_ports {sdio_sdwp}]
 #set_property -dict { PACKAGE_PIN AP32  IOSTANDARD LVCMOS18 } [get_ports {sdio_sddet}]
 set_property -dict { PACKAGE_PIN AN30  IOSTANDARD LVCMOS18  IOB TRUE } [get_ports {sdio_clk}]
 set_property -dict { PACKAGE_PIN AP30  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_cmd}]
 set_property -dict { PACKAGE_PIN AR30  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[0]}]
 set_property -dict { PACKAGE_PIN AU31  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[1]}]
 set_property -dict { PACKAGE_PIN AV31  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[2]}]
 set_property -dict { PACKAGE_PIN AT30  IOSTANDARD LVCMOS18  IOB TRUE  PULLUP TRUE } [get_ports {sdio_dat[3]}]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up_d"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_cs*"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/pcie_bme"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/arready_int"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/en_barhit"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_ns*"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/illegal_burst_int"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_req_sent"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/slot_request"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/open_slot"]
 #set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
 #set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_2/state*"]
 #set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_1_1/*acquire*"]
 #set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/io_*"]
 set_clock_groups -asynchronous \
  -group [list \
     [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]] \
  -group [list \
     [get_clocks -include_generated_clocks -of_objects [get_ports sys_diff_clock_clk_p]]]
--- a/fpga/u500vc707devkit/script/board.tcl
+++ b/fpga/u500vc707devkit/script/board.tcl
@ -1,5 +0,0 @@
 # See LICENSE for license details.
 set name {vc707}
 set part_fpga {xc7vx485tffg1761-2}
 set part_board {xilinx.com:vc707:part0:1.3} 
 set bootrom_inst {rom}
--- a/fpga/u500vc707devkit/script/cfgmem.tcl
+++ b/fpga/u500vc707devkit/script/cfgmem.tcl
@ -1,10 +0,0 @@
 lassign $argv mcsfile bitfile datafile
 set iface bpix16
 set size 128
 set bitaddr 0x3000000
 write_cfgmem -format mcs -interface $iface -size $size \
  -loadbit "up ${bitaddr} ${bitfile}" \
  -loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
  -file $mcsfile -force
--- a/fpga/u500vc707devkit/script/impl.tcl
+++ b/fpga/u500vc707devkit/script/impl.tcl
@ -1,53 +0,0 @@
 set_param {messaging.defaultLimit} 1000000
 read_ip [glob -directory $ipdir [file join * {*.xci}]]
 synth_design -top $top -flatten_hierarchy rebuilt
 write_checkpoint -force [file join $wrkdir post_synth]
 opt_design
 write_checkpoint -force [file join $wrkdir post_opt]
 place_design
 write_checkpoint -force [file join $wrkdir post_place]
 phys_opt_design
 power_opt_design
 route_design
 write_checkpoint -force [file join $wrkdir post_route]
 write_bitstream -force [file join $wrkdir "${top}.bit"]
 write_sdf -force [file join $wrkdir "${top}.sdf"]
 write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
 write_debug_probes -force [file join $wrkdir "${top}.ltx"]
 # AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
 # Work around the write_mem_info command not supporting "processor-less"
 # (non-Microblaze) designs.
 set bram_inst [get_cells -hierarchical "bram"]
 if {$bram_inst ne ""} {
  source [file join $scriptdir "bram.tcl"]
  write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
 }
 if {[info exists bootrom_inst]} {
  puts "Generating bootrom.mmi ..."
  set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
  if {$rom_inst ne ""} {
    source [file join $scriptdir "bram.tcl"]
    write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
  }
 }
 set rptdir [file join $wrkdir report]
 file mkdir $rptdir
 set rptutil [file join $rptdir utilization.txt]
 report_datasheet -file [file join $rptdir datasheet.txt]
 report_utilization -hierarchical -file $rptutil
 report_clock_utilization -file $rptutil -append
 report_ram_utilization -file $rptutil -append -detail
 report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
 report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
 report_drc -file [file join $rptdir drc.txt]
 report_io -file [file join $rptdir io.txt]
 report_clocks -file [file join $rptdir clocks.txt]
--- a/fpga/u500vc707devkit/script/init.tcl
+++ b/fpga/u500vc707devkit/script/init.tcl
@ -1,41 +0,0 @@
 proc recglob { basedir pattern } {
  set dirlist [glob -nocomplain -directory $basedir -type d *]
  set findlist [glob -nocomplain -directory $basedir $pattern]
  foreach dir $dirlist {
    set reclist [recglob $dir $pattern]
    set findlist [concat $findlist $reclist]
  }
  return $findlist
 }
 proc findincludedir { basedir pattern } {
  #find all subdirectories containing ".vh" files
  set vhfiles [recglob $basedir $pattern]
  set vhdirs {}
  foreach match $vhfiles {
    lappend vhdirs [file dir $match]
  }
  set uniquevhdirs [lsort -unique $vhdirs]
  return $uniquevhdirs
 }
 file mkdir $ipdir
 update_ip_catalog -rebuild
 source [file join $scriptdir ip.tcl]
 # AR 58526 <http://www.xilinx.com/support/answers/58526.html>
 set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
 set obj [get_ips]
 generate_target all $obj
 export_ip_user_files -of_objects $obj -no_script -force
 set obj [current_fileset]
 # Xilinx bug workaround
 # scrape IP tree for directories containing .vh files
 # [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
 set property_include_dirs [get_property include_dirs $obj]
 set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
 set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
 set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
--- a/fpga/u500vc707devkit/script/ip.tcl
+++ b/fpga/u500vc707devkit/script/ip.tcl
@ -1,97 +0,0 @@
 #MIG
 create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc707mig -dir $ipdir -force
 set migprj [file join [pwd] $scriptdir {mig.prj}] 
 set_property CONFIG.XML_INPUT_FILE $migprj [get_ips vc707mig]
 puts "SCRIPTDIR $scriptdir"
 #AXI_PCIE
 create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
 set_property -dict [list \
 CONFIG.AXIBAR2PCIEBAR_0             {0x60000000} \
 CONFIG.AXIBAR2PCIEBAR_1             {0x00000000} \
 CONFIG.AXIBAR2PCIEBAR_2             {0x00000000} \
 CONFIG.AXIBAR2PCIEBAR_3             {0x00000000} \
 CONFIG.AXIBAR2PCIEBAR_4             {0x00000000} \
 CONFIG.AXIBAR2PCIEBAR_5             {0x00000000} \
 CONFIG.AXIBAR_0                     {0x60000000} \
 CONFIG.AXIBAR_1                     {0xFFFFFFFF} \
 CONFIG.AXIBAR_2                     {0xFFFFFFFF} \
 CONFIG.AXIBAR_3                     {0xFFFFFFFF} \
 CONFIG.AXIBAR_4                     {0xFFFFFFFF} \
 CONFIG.AXIBAR_5                     {0xFFFFFFFF} \
 CONFIG.AXIBAR_AS_0                  {true} \
 CONFIG.AXIBAR_AS_1                  {false} \
 CONFIG.AXIBAR_AS_2                  {false} \
 CONFIG.AXIBAR_AS_3                  {false} \
 CONFIG.AXIBAR_AS_4                  {false} \
 CONFIG.AXIBAR_AS_5                  {false} \
 CONFIG.AXIBAR_HIGHADDR_0            {0x7FFFFFFF} \
 CONFIG.AXIBAR_HIGHADDR_1            {0x00000000} \
 CONFIG.AXIBAR_HIGHADDR_2            {0x00000000} \
 CONFIG.AXIBAR_HIGHADDR_3            {0x00000000} \
 CONFIG.AXIBAR_HIGHADDR_4            {0x00000000} \
 CONFIG.AXIBAR_HIGHADDR_5            {0x00000000} \
 CONFIG.AXIBAR_NUM                   {1} \
 CONFIG.BAR0_ENABLED                 {true} \
 CONFIG.BAR0_SCALE                   {Gigabytes} \
 CONFIG.BAR0_SIZE                    {4} \
 CONFIG.BAR0_TYPE                    {Memory} \
 CONFIG.BAR1_ENABLED                 {false} \
 CONFIG.BAR1_SCALE                   {N/A} \
 CONFIG.BAR1_SIZE                    {8} \
 CONFIG.BAR1_TYPE                    {N/A} \
 CONFIG.BAR2_ENABLED                 {false} \
 CONFIG.BAR2_SCALE                   {N/A} \
 CONFIG.BAR2_SIZE                    {8} \
 CONFIG.BAR2_TYPE                    {N/A} \
 CONFIG.BAR_64BIT                    {true} \
 CONFIG.BASEADDR                     {0x50000000} \
 CONFIG.BASE_CLASS_MENU              {Bridge_device} \
 CONFIG.CLASS_CODE                   {0x060400} \
 CONFIG.COMP_TIMEOUT                 {50us} \
 CONFIG.Component_Name               {design_1_axi_pcie_1_0} \
 CONFIG.DEVICE_ID                    {0x7111} \
 CONFIG.ENABLE_CLASS_CODE            {true} \
 CONFIG.HIGHADDR                     {0x53FFFFFF} \
 CONFIG.INCLUDE_BAROFFSET_REG        {true} \
 CONFIG.INCLUDE_RC                   {Root_Port_of_PCI_Express_Root_Complex} \
 CONFIG.INTERRUPT_PIN                {false} \
 CONFIG.MAX_LINK_SPEED               {2.5_GT/s} \
 CONFIG.MSI_DECODE_ENABLED           {true} \
 CONFIG.M_AXI_ADDR_WIDTH             {32} \
 CONFIG.M_AXI_DATA_WIDTH             {64} \
 CONFIG.NO_OF_LANES                  {X1} \
 CONFIG.NUM_MSI_REQ                  {0} \
 CONFIG.PCIEBAR2AXIBAR_0_SEC         {1} \
 CONFIG.PCIEBAR2AXIBAR_0             {0x00000000} \
 CONFIG.PCIEBAR2AXIBAR_1             {0xFFFFFFFF} \
 CONFIG.PCIEBAR2AXIBAR_1_SEC         {1} \
 CONFIG.PCIEBAR2AXIBAR_2             {0xFFFFFFFF} \
 CONFIG.PCIEBAR2AXIBAR_2_SEC         {1} \
 CONFIG.PCIE_BLK_LOCN                {X1Y1} \
 CONFIG.PCIE_USE_MODE                {GES_and_Production} \
 CONFIG.REF_CLK_FREQ                 {100_MHz} \
 CONFIG.REV_ID                       {0x00} \
 CONFIG.SLOT_CLOCK_CONFIG            {true} \
 CONFIG.SUBSYSTEM_ID                 {0x0007} \
 CONFIG.SUBSYSTEM_VENDOR_ID          {0x10EE} \
 CONFIG.SUB_CLASS_INTERFACE_MENU     {Host_bridge} \
 CONFIG.S_AXI_ADDR_WIDTH             {32} \
 CONFIG.S_AXI_DATA_WIDTH             {64} \
 CONFIG.S_AXI_ID_WIDTH               {4} \
 CONFIG.S_AXI_SUPPORTS_NARROW_BURST  {false} \
 CONFIG.VENDOR_ID                    {0x10EE} \
 CONFIG.XLNX_REF_BOARD               {None} \
 CONFIG.axi_aclk_loopback            {false} \
 CONFIG.en_ext_ch_gt_drp             {false} \
 CONFIG.en_ext_clk                   {false} \
 CONFIG.en_ext_gt_common             {false} \
 CONFIG.en_ext_pipe_interface        {false} \
 CONFIG.en_transceiver_status_ports  {false} \
 CONFIG.no_slv_err                   {false} \
 CONFIG.rp_bar_hide                  {true} \
 CONFIG.shared_logic_in_core         {false} ] [get_ips vc707axi_to_pcie_x1]
--- a/fpga/u500vc707devkit/script/mig.prj
+++ b/fpga/u500vc707devkit/script/mig.prj
@ -1,202 +0,0 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
 <Project NoOfControllers="1" >
    <ModuleName>vc707mig</ModuleName>
    <dci_inouts_inputs>1</dci_inouts_inputs>
    <dci_inputs>1</dci_inputs>
    <Debug_En>OFF</Debug_En>
    <DataDepth_En>1024</DataDepth_En>
    <LowPower_En>ON</LowPower_En>
    <XADC_En>Enabled</XADC_En>
    <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
    <Version>3.0</Version>
    <SystemClock>Differential</SystemClock>
    <ReferenceClock>Use System Clock</ReferenceClock>
    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
    <BankSelectionFlag>FALSE</BankSelectionFlag>
    <InternalVref>0</InternalVref>
    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
    <dci_cascade>0</dci_cascade>
    <Controller number="0" >
        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
        <TimePeriod>1250</TimePeriod>
        <VccAuxIO>2.0V</VccAuxIO>
        <PHYRatio>4:1</PHYRatio>
        <InputClkFreq>200</InputClkFreq>
        <UIExtraClocks>0</UIExtraClocks>
        <MMCM_VCO>800</MMCM_VCO>
        <MMCMClkOut0> 1.000</MMCMClkOut0>
        <MMCMClkOut1>1</MMCMClkOut1>
        <MMCMClkOut2>1</MMCMClkOut2>
        <MMCMClkOut3>1</MMCMClkOut3>
        <MMCMClkOut4>1</MMCMClkOut4>
        <DataWidth>64</DataWidth>
        <DeepMemory>1</DeepMemory>
        <DataMask>1</DataMask>
        <ECC>Disabled</ECC>
        <Ordering>Normal</Ordering>
        <CustomPart>FALSE</CustomPart>
        <NewPartName></NewPartName>
        <RowAddress>14</RowAddress>
        <ColAddress>10</ColAddress>
        <BankAddress>3</BankAddress>
        <MemoryVoltage>1.5V</MemoryVoltage>
        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
        <PinSelection>
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
        </PinSelection>
        <System_Clock>
            <Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
        </System_Clock>
        <System_Control>
            <Pin PADName="AV40" Bank="15" name="sys_rst" />
            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
        </System_Control>
        <TimingParameters>
            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
        </TimingParameters>
        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
        <mrCasLatency name="CAS Latency" >11</mrCasLatency>
        <mrMode name="Mode" >Normal</mrMode>
        <mrDllReset name="DLL Reset" >No</mrDllReset>
        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
        <emrDQS name="TDQS enable" >Enabled</emrDQS>
        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
        <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
        <PortInterface>AXI</PortInterface>
        <AXIParameters>
            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
            <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
            <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
        </AXIParameters>
    </Controller>
 </Project>
--- a/fpga/u500vc707devkit/script/prologue.tcl
+++ b/fpga/u500vc707devkit/script/prologue.tcl
@ -1,69 +0,0 @@
 set scriptdir [file dirname [info script]]
 set commondir [file dirname $scriptdir]
 set srcdir [file join $commondir src]
 set constrsdir [file join $commondir constrs]
 set wrkdir [file join [pwd] obj]
 set ipdir [file join $wrkdir ip]
 set top {system}
 create_project -part $part_fpga -in_memory
 set_property -dict [list \
  BOARD_PART $part_board \
  TARGET_LANGUAGE {Verilog} \
  SIMULATOR_LANGUAGE {Mixed} \
  TARGET_SIMULATOR {XSim} \
  DEFAULT_LIB {xil_defaultlib} \
  IP_REPO_PATHS $ipdir \
  ] [current_project]
 proc recglob { basedir pattern } {
  set dirlist [glob -nocomplain -directory $basedir -type d *]
  set findlist [glob -nocomplain -directory $basedir $pattern]
  foreach dir $dirlist {
    set reclist [recglob $dir $pattern]
    set findlist [concat $findlist $reclist]
  }
  return $findlist
 }
 if {[get_filesets -quiet sources_1] eq ""} {
  create_fileset -srcset sources_1
 }
 set obj [current_fileset]
 set srcmainverilogfiles [recglob $srcdir "*.v"]
 add_files -norecurse -fileset $obj $srcmainverilogfiles
 if {[info exists ::env(EXTRA_VSRCS)]} {
  set extra_vsrcs [split $::env(EXTRA_VSRCS)]
  foreach extra_vsrc $extra_vsrcs {
    add_files -norecurse -fileset $obj $extra_vsrc
  }
 }
 ## TODO: These paths and files should come from the caller, not within this script.
 #if {[file exists [file join $srcdir include verilog]]} {
 #  add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
 #  add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
 #}
 set vsrc_top $::env(VSRC_TOP)
 set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
 add_files -norecurse -fileset $obj $vsrc_top
 if {[get_filesets -quiet sim_1] eq ""} {
  create_fileset -simset sim_1
 }
 set obj [current_fileset -simset]
 add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
 set_property TOP {tb} $obj
 if {[get_filesets -quiet constrs_1] eq ""} {
  create_fileset -constrset constrs_1
 }
 set obj [current_fileset -constrset]
 add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
--- a/fpga/u500vc707devkit/src/sdio.v
+++ b/fpga/u500vc707devkit/src/sdio.v
@ -1,59 +0,0 @@
 // See LICENSE for license details.
 `timescale 1ns/1ps
 `default_nettype none
 module sdio_spi_bridge (
  input wire clk,
  input wire reset,
  // SDIO
  inout  wire       sd_cmd,
  inout  wire [3:0] sd_dat,
  output wire       sd_sck,
  // QUAD SPI
  input  wire       spi_sck,
  input  wire [3:0] spi_dq_o,
  output wire [3:0] spi_dq_i,
  output wire       spi_cs
 );
  wire mosi, miso;
  reg miso_sync [1:0];
  assign mosi = spi_dq_o[0];
  assign spi_dq_i = {2'b00, miso_sync[1], 1'b0};
  assign sd_sck = spi_sck;
  IOBUF buf_cmd (
    .IO(sd_cmd),
    .I(mosi),
    .O(),
    .T(1'b0)
  );
  IOBUF buf_dat0 (
    .IO(sd_dat[0]),
    .I(),
    .O(miso),
    .T(1'b1)
  );
  IOBUF buf_dat3 (
    .IO(sd_dat[3]),
    .I(spi_cs),
    .O(),
    .T(1'b0)
  );
  always @(posedge clk) begin
    if (reset) begin
       miso_sync[0] <= 1'b0;
       miso_sync[1] <= 1'b0;
    end else begin
       miso_sync[0] <= miso;
       miso_sync[1] <= miso_sync[0];
    end
  end
 endmodule
 `default_nettype wire
--- a/fpga/u500vc707devkit/src/system.v
+++ b/fpga/u500vc707devkit/src/system.v
@ -1,168 +0,0 @@
 // See LICENSE for license details.
 `timescale 1ns/1ps
 `default_nettype none
 module system
 (
  //200Mhz differential sysclk
  input  wire sys_diff_clock_clk_n,
  input  wire sys_diff_clock_clk_p,
  //active high reset
  input  wire reset,
  // DDR3 SDRAM
  output wire [13:0] ddr3_addr,
  output wire [2:0]  ddr3_ba,
  output wire        ddr3_cas_n,
  output wire [0:0]  ddr3_ck_n,
  output wire [0:0]  ddr3_ck_p,
  output wire [0:0]  ddr3_cke,
  output wire [0:0]  ddr3_cs_n,
  output wire [7:0]  ddr3_dm,
  inout  wire [63:0] ddr3_dq,
  inout  wire [7:0]  ddr3_dqs_n,
  inout  wire [7:0]  ddr3_dqs_p,
  output wire [0:0]  ddr3_odt,
  output wire        ddr3_ras_n,
  output wire        ddr3_reset_n,
  output wire        ddr3_we_n,
  // LED
  output wire [7:0] led,
  //UART
  output wire uart_tx,
  input  wire uart_rx,
  output wire uart_rtsn,
  input  wire uart_ctsn,
  //SDIO
  output wire       sdio_clk,
  inout  wire       sdio_cmd,
  inout  wire [3:0] sdio_dat,
  //JTAG
  input  wire       jtag_TCK,
  input  wire       jtag_TMS,
  input  wire       jtag_TDI,
  output wire       jtag_TDO,
  //PCIe
  output wire [0:0] pci_exp_txp,
  output wire [0:0] pci_exp_txn,
  input  wire [0:0] pci_exp_rxp,
  input  wire [0:0] pci_exp_rxn,
  input  wire       pci_exp_refclk_rxp,
  input  wire       pci_exp_refclk_rxn
 );
 reg [1:0] uart_rx_sync;
 wire [3:0] sd_spi_dq_i;
 wire [3:0] sd_spi_dq_o;
 wire sd_spi_sck;
 wire sd_spi_cs;
 wire top_clock,top_reset;
 U500VC707DevKitTop top
 (
  //UART
  .io_uarts_0_rxd(uart_rx_sync[1]),
  .io_uarts_0_txd(uart_tx),
  //SPI
  .io_spis_0_sck(sd_spi_sck),
  .io_spis_0_dq_0_i(sd_spi_dq_i[0]),
  .io_spis_0_dq_1_i(sd_spi_dq_i[1]),
  .io_spis_0_dq_2_i(sd_spi_dq_i[2]),
  .io_spis_0_dq_3_i(sd_spi_dq_i[3]),
  .io_spis_0_dq_0_o(sd_spi_dq_o[0]),
  .io_spis_0_dq_1_o(sd_spi_dq_o[1]),
  .io_spis_0_dq_2_o(sd_spi_dq_o[2]),
  .io_spis_0_dq_3_o(sd_spi_dq_o[3]),
  .io_spis_0_dq_0_oe(),
  .io_spis_0_dq_1_oe(),
  .io_spis_0_dq_2_oe(),
  .io_spis_0_dq_3_oe(),
  .io_spis_0_cs_0(sd_spi_cs),
  //GPIO
  .io_gpio_pins_0_i_ival(1'b0),
  .io_gpio_pins_1_i_ival(1'b0),
  .io_gpio_pins_2_i_ival(1'b0),
  .io_gpio_pins_3_i_ival(1'b0),
  .io_gpio_pins_0_o_oval(led[0]),
  .io_gpio_pins_1_o_oval(led[1]),
  .io_gpio_pins_2_o_oval(led[2]),
  .io_gpio_pins_3_o_oval(led[3]),
  .io_gpio_pins_0_o_oe(),
  .io_gpio_pins_1_o_oe(),
  .io_gpio_pins_2_o_oe(),
  .io_gpio_pins_3_o_oe(),
  .io_gpio_pins_0_o_pue(),
  .io_gpio_pins_1_o_pue(),
  .io_gpio_pins_2_o_pue(),
  .io_gpio_pins_3_o_pue(),
  .io_gpio_pins_0_o_ds(),
  .io_gpio_pins_1_o_ds(),
  .io_gpio_pins_2_o_ds(),
  .io_gpio_pins_3_o_ds(),
  //JTAG
  .io_jtag_TRST(1'b0),
  .io_jtag_TCK(jtag_TCK),
  .io_jtag_TMS(jtag_TMS),
  .io_jtag_TDI(jtag_TDI),
  .io_jtag_DRV_TDO(),
  .io_jtag_TDO(jtag_TDO),
  //MIG
  .io_xilinxvc707mig__inout_ddr3_dq(ddr3_dq),
  .io_xilinxvc707mig__inout_ddr3_dqs_n(ddr3_dqs_n),
  .io_xilinxvc707mig__inout_ddr3_dqs_p(ddr3_dqs_p),
  .io_xilinxvc707mig_ddr3_addr(ddr3_addr),
  .io_xilinxvc707mig_ddr3_ba(ddr3_ba),
  .io_xilinxvc707mig_ddr3_ras_n(ddr3_ras_n),
  .io_xilinxvc707mig_ddr3_cas_n(ddr3_cas_n),
  .io_xilinxvc707mig_ddr3_we_n(ddr3_we_n),
  .io_xilinxvc707mig_ddr3_reset_n(ddr3_reset_n),
  .io_xilinxvc707mig_ddr3_ck_p(ddr3_ck_p),
  .io_xilinxvc707mig_ddr3_ck_n(ddr3_ck_n),
  .io_xilinxvc707mig_ddr3_cke(ddr3_cke),
  .io_xilinxvc707mig_ddr3_cs_n(ddr3_cs_n),
  .io_xilinxvc707mig_ddr3_dm(ddr3_dm),
  .io_xilinxvc707mig_ddr3_odt(ddr3_odt),
  //PCIe
  .io_xilinxvc707pcie_pci_exp_txp(pci_exp_txp),
  .io_xilinxvc707pcie_pci_exp_txn(pci_exp_txn),
  .io_xilinxvc707pcie_pci_exp_rxp(pci_exp_rxp),
  .io_xilinxvc707pcie_pci_exp_rxn(pci_exp_rxn),
  //Clock + Reset
  .io_pcie_refclk_p(pci_exp_refclk_rxp),
  .io_pcie_refclk_n(pci_exp_refclk_rxn),
  .io_sys_clk_p(sys_diff_clock_clk_p),
  .io_sys_clk_n(sys_diff_clock_clk_n),
  .io_sys_reset(reset),
  //Misc outputs for system.v
  .io_core_clock(top_clock),
  .io_core_reset(top_reset)
 );
  sdio_spi_bridge ip_sdio_spi
  (
   .clk(top_clock),
   .reset(top_reset),
   .sd_cmd(sdio_cmd),
   .sd_dat(sdio_dat),
   .sd_sck(sdio_clk),
   .spi_sck(sd_spi_sck),
   .spi_dq_o(sd_spi_dq_o),
   .spi_dq_i(sd_spi_dq_i),
   .spi_cs(sd_spi_cs)
  );
  //UART
  assign uart_rtsn =1'b0;  
  always @(posedge top_clock) begin
    if (top_reset) begin
      uart_rx_sync <= 2'b11;
    end else begin
      uart_rx_sync[0] <= uart_rx;
      uart_rx_sync[1] <= uart_rx_sync[0];
    end
  end
  assign led[7:4] = 4'b0000;
 endmodule
 `default_nettype wire
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 4146f6a792277297bd80d4b6f1b6f2b3cb0f31d7
+Subproject commit 82df766f4a5b1efb24b8659eb11c8b12c410a291
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 7916ef5249c72a3a84c599d123760f4d716de58a
+Subproject commit f266b55da92e42350be5704b4fe7d2a934e986ae
--- a/src/main/scala/everywhere/e300artydevkit/Config.scala
+++ b/src/main/scala/everywhere/e300artydevkit/Config.scala
@ -0,0 +1,65 @@
 // See LICENSE for license details.
 package sifive.freedom.everywhere.e300artydevkit
 import freechips.rocketchip.config._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._
 import sifive.blocks.devices.mockaon._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.pwm._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.i2c._
 // Default FreedomEConfig
 class DefaultFreedomEConfig extends Config (
  new WithNBreakpoints(2)        ++
  new WithNExtTopInterrupts(0)   ++
  new WithJtagDTM                ++
  new TinyConfig
 )
 // Freedom E300 Arty Dev Kit Peripherals
 class E300DevKitPeripherals extends Config((site, here, up) => {
  case PeripheryGPIOKey => List(
    GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
  case PeripheryPWMKey => List(
    PWMParams(address = 0x10015000, cmpWidth = 8),
    PWMParams(address = 0x10025000, cmpWidth = 16),
    PWMParams(address = 0x10035000, cmpWidth = 16))
  case PeripherySPIKey => List(
    SPIParams(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
    SPIParams(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
  case PeripherySPIFlashKey => List(
    SPIFlashParams(
      fAddress = 0x20000000,
      rAddress = 0x10014000,
      sampleDelay = 3))
  case PeripheryUARTKey => List(
    UARTParams(address = 0x10013000),
    UARTParams(address = 0x10023000))
  case PeripheryI2CKey => List(
    I2CParams(address = 0x10016000))
  case PeripheryMockAONKey =>
    MockAONParams(address = 0x10000000)
  case PeripheryMaskROMKey => List(
    MaskROMParams(address = 0x10000, name = "BootROM"))
 })
 // Freedom E300 Arty Dev Kit Peripherals
 class E300ArtyDevKitConfig extends Config(
  new E300DevKitPeripherals    ++
  new DefaultFreedomEConfig().alter((site,here,up) => {
    case DTSTimebase => BigInt(32768)
    case JtagDTMKey => new JtagDTMConfig (
      idcodeVersion = 2,
      idcodePartNum = 0x000,
      idcodeManufId = 0x489,
      debugIdleCycles = 5)
  })
 )
--- a/src/main/scala/everywhere/e300artydevkit/Configs.scala
+++ b/src/main/scala/everywhere/e300artydevkit/Configs.scala
@ -1,37 +0,0 @@
 // See LICENSE for license details.
 package sifive.freedom.everywhere.e300artydevkit
 import config._
 import coreplex._
 import rocketchip._
 class DefaultFreedomEConfig extends Config(
  new WithStatelessBridge        ++
  new WithNBreakpoints(2)        ++
  new WithRV32                   ++
  new DefaultSmallConfig
 )
 class WithBootROMFile(bootROMFile: String) extends Config(
  (pname, site, here) => pname match {
    case BootROMFile => bootROMFile
    case _ => throw new CDEMatchError
  }
 )
 class E300ArtyDevKitConfig extends Config(
  new WithBootROMFile("./bootrom/e300artydevkit.img") ++
  new WithNExtTopInterrupts(0) ++
  new WithJtagDTM ++
  new WithL1ICacheSets(8192/32) ++ // 8 KiB **per set**
  new WithCacheBlockBytes(32) ++
  new WithL1ICacheWays(2) ++
  new WithDefaultBtb ++
  new WithFastMulDiv ++
  new WithDataScratchpad(16384) ++
  new WithNMemoryChannels(0) ++
  new WithoutFPU ++
  new WithTLMonitors ++
  new DefaultFreedomEConfig
 )
--- a/src/main/scala/everywhere/e300artydevkit/FPGAChip.scala
+++ b/src/main/scala/everywhere/e300artydevkit/FPGAChip.scala
@ -0,0 +1,193 @@
 // See LICENSE for license details.
 package sifive.freedom.everywhere.e300artydevkit
 import Chisel._
 import chisel3.core.{attach}
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy.{LazyModule}
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
 //-------------------------------------------------------------------------
 // E300ArtyDevKitFPGAChip
 //-------------------------------------------------------------------------
 class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell {
  //-----------------------------------------------------------------------
  // Clock divider
  //-----------------------------------------------------------------------
  val slow_clock = Wire(Bool())
  // Divide clock by 256, used to generate 32.768 kHz clock for AON block
  withClockAndReset(clock_8MHz, ~mmcm_locked) {
    val clockToggleReg = RegInit(false.B)
    val (_, slowTick) = Counter(true.B, 256)
    when (slowTick) {clockToggleReg := ~clockToggleReg}
    slow_clock := clockToggleReg
  }
  //-----------------------------------------------------------------------
  // DUT
  //-----------------------------------------------------------------------
  withClockAndReset(clock_32MHz, ck_rst) {
    val dut = Module(new E300ArtyDevKitPlatform)
    //---------------------------------------------------------------------
    // SPI flash IOBUFs
    //---------------------------------------------------------------------
    IOBUF(qspi_sck, dut.io.pins.qspi.sck)
    IOBUF(qspi_cs,  dut.io.pins.qspi.cs(0))
    IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0))
    IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1))
    IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2))
    IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3))
    //---------------------------------------------------------------------
    // JTAG IOBUFs
    //---------------------------------------------------------------------
    dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt
    IOBUF(jd_5, dut.io.pins.jtag.TMS)
    PULLUP(jd_5)
    IOBUF(jd_4, dut.io.pins.jtag.TDI)
    PULLUP(jd_4)
    IOBUF(jd_0, dut.io.pins.jtag.TDO)
    // mimic putting a pullup on this line (part of reset vote)
    SRST_n := IOBUF(jd_6)
    PULLUP(jd_6)
    // jtag reset
    val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz)
    dut.io.jtag_reset := jtag_power_on_reset
    // debug reset
    dut_ndreset := dut.io.ndreset
    //---------------------------------------------------------------------
    // Assignment to package pins
    //---------------------------------------------------------------------
    // Pins IO0-IO13
    //
    // FTDI UART TX/RX are not connected to ck_io[0,1]
    // the way they are on Arduino boards.  We copy outgoing
    // data to both places, switch 3 (sw[3]) determines whether
    // input to UART comes from FTDI chip or gpio_16 (shield pin PD0)
    val iobuf_ck0 = Module(new IOBUF())
    iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval
    iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe
    attach(iobuf_ck0.io.IO, ck_io(0))   // UART0 RX
    val iobuf_uart_txd = Module(new IOBUF())
    iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval
    iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe
    attach(iobuf_uart_txd.io.IO, uart_txd_in)
    // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3]
    val sw_3_in = IOBUF(sw_3)
    dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in,
                                            iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie,
                                            iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie)
    IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17))
    // Shield header row 0: PD2-PD7
    IOBUF(ck_io(2),  dut.io.pins.gpio.pins(18))
    IOBUF(ck_io(3),  dut.io.pins.gpio.pins(19)) // PWM1(1)
    IOBUF(ck_io(4),  dut.io.pins.gpio.pins(20)) // PWM1(0)
    IOBUF(ck_io(5),  dut.io.pins.gpio.pins(21)) // PWM1(2)
    IOBUF(ck_io(6),  dut.io.pins.gpio.pins(22)) // PWM1(3)
    IOBUF(ck_io(7),  dut.io.pins.gpio.pins(23))
    // Header row 1: PB0-PB5
    IOBUF(ck_io(8),  dut.io.pins.gpio.pins(0))  // PWM0(0)
    IOBUF(ck_io(9),  dut.io.pins.gpio.pins(1))  // PWM0(1)
    IOBUF(ck_io(10), dut.io.pins.gpio.pins(2))  // SPI CS(0) / PWM0(2)
    IOBUF(ck_io(11), dut.io.pins.gpio.pins(3))  // SPI MOSI  / PWM0(3)
    IOBUF(ck_io(12), dut.io.pins.gpio.pins(4))  // SPI MISO
    IOBUF(ck_io(13), dut.io.pins.gpio.pins(5))  // SPI SCK
    dut.io.pins.gpio.pins(6).i.ival  := 0.U
    dut.io.pins.gpio.pins(7).i.ival  := 0.U
    dut.io.pins.gpio.pins(8).i.ival  := 0.U
    // Header row 3: A0-A5 (we don't support using them as analog inputs)
    // just treat them as regular digital GPIOs
    IOBUF(ck_io(15), dut.io.pins.gpio.pins(9))  // A1 = CS(2)
    IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0)
    IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1)
    IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA
    IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL
    // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty
    // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active
    IOBUF(led0_r, dut.io.pins.gpio.pins(1))
    IOBUF(led0_g, dut.io.pins.gpio.pins(2))
    IOBUF(led0_b, dut.io.pins.gpio.pins(3))
    // Note that this is the one which is actually connected on the HiFive/Crazy88
    // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active
    IOBUF(led1_r, dut.io.pins.gpio.pins(19))
    IOBUF(led1_g, dut.io.pins.gpio.pins(21))
    IOBUF(led1_b, dut.io.pins.gpio.pins(22))
    // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active
    IOBUF(led2_r, dut.io.pins.gpio.pins(11))
    IOBUF(led2_g, dut.io.pins.gpio.pins(12))
    IOBUF(led2_b, dut.io.pins.gpio.pins(13))
    // Only 19 out of 20 shield pins connected to GPIO pins
    // Shield pin A5 (pin 14) left unconnected
    // The buttons are connected to some extra GPIO pins not connected on the
    // HiFive1 board
    IOBUF(btn_0, dut.io.pins.gpio.pins(15))
    IOBUF(btn_1, dut.io.pins.gpio.pins(30))
    IOBUF(btn_2, dut.io.pins.gpio.pins(31))
    val iobuf_btn_3 = Module(new IOBUF())
    iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval
    iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe
    attach(btn_3, iobuf_btn_3.io.IO)
    dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie
    // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1
    IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX
    IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX
    // SPI2 pins mapped to 6 pin ICSP connector (standard on later
    // arduinos) These are connected to some extra GPIO pins not connected
    // on the HiFive1 board
    IOBUF(ck_ss,   dut.io.pins.gpio.pins(26))
    IOBUF(ck_mosi, dut.io.pins.gpio.pins(27))
    IOBUF(ck_miso, dut.io.pins.gpio.pins(28))
    IOBUF(ck_sck,  dut.io.pins.gpio.pins(29))
    // Use the LEDs for some more useful debugging things
    IOBUF(led_0, ck_rst)
    IOBUF(led_1, SRST_n)
    IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival)
    IOBUF(led_3, dut.io.pins.gpio.pins(14))
    //---------------------------------------------------------------------
    // Unconnected inputs
    //---------------------------------------------------------------------
    dut.io.pins.aon.erst_n.i.ival       := ~reset_periph
    dut.io.pins.aon.lfextclk.i.ival     := slow_clock
    dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U
  }
 }
--- a/src/main/scala/everywhere/e300artydevkit/Platform.scala
+++ b/src/main/scala/everywhere/e300artydevkit/Platform.scala
@ -0,0 +1,177 @@
 // See LICENSE for license details.
 package sifive.freedom.everywhere.e300artydevkit
 import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.system._
 import sifive.blocks.util.{ResetCatchAndSync}
 import sifive.blocks.devices.mockaon._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.jtag._
 import sifive.blocks.devices.pwm._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.i2c._
 import sifive.blocks.devices.pinctrl._
 //-------------------------------------------------------------------------
 // PinGen
 //-------------------------------------------------------------------------
 object PinGen {
  def apply(): BasePin =  {
    val pin = new BasePin()
    pin
  }
 }
 //-------------------------------------------------------------------------
 // E300ArtyDevKitPlatformIO
 //-------------------------------------------------------------------------
 class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
  val pins = new Bundle {
    val jtag = new JTAGPins(() => PinGen(), false)
    val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))
    val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))
    val aon = new MockAONWrapperPins()
  }
  val jtag_reset = Bool(INPUT)
  val ndreset    = Bool(OUTPUT)
 }
 //-------------------------------------------------------------------------
 // E300ArtyDevKitPlatform
 //-------------------------------------------------------------------------
 class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
  val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
  val io = new E300ArtyDevKitPlatformIO
  // This needs to be de-asserted synchronously to the coreClk.
  val async_corerst = sys.aon.rsts.corerst
  // Add in debug-controlled reset.
  sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
  //-----------------------------------------------------------------------
  // Check for unsupported rocket-chip connections
  //-----------------------------------------------------------------------
  require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
  //-----------------------------------------------------------------------
  // Build GPIO Pin Mux
  //-----------------------------------------------------------------------
  // Pin Mux for UART, SPI, PWM
  // First convert the System outputs into "IOF" using the respective *GPIOPort
  // converters.
  val sys_uart = sys.uart
  val sys_pwm  = sys.pwm
  val sys_spi  = sys.spi
  val sys_i2c  = sys.i2c
  val uart_pins = sys.outer.uartParams.map { c => Wire(new UARTPins(() => PinGen()))}
  val pwm_pins  = sys.outer.pwmParams.map  { c => Wire(new PWMPins(() => PinGen(), c))}
  val spi_pins  = sys.outer.spiParams.map  { c => Wire(new SPIPins(() => PinGen(), c))}
  val i2c_pins  = sys.outer.i2cParams.map  { c => Wire(new I2CPins(() => PinGen()))}
  (uart_pins zip  sys_uart) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
  (pwm_pins  zip  sys_pwm)  map {case (p, r) => p.fromPort(r)}
  (spi_pins  zip  sys_spi)  map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
  (i2c_pins  zip  sys_i2c)  map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
  //-----------------------------------------------------------------------
  // Default Pin connections before attaching pinmux
  for (iof_0 <- sys.gpio(0).iof_0.get) {
    iof_0.default()
  }
  for (iof_1 <- sys.gpio(0).iof_1.get) {
    iof_1.default()
  }
  //-----------------------------------------------------------------------
  val iof_0 = sys.gpio(0).iof_0.get
  val iof_1 = sys.gpio(0).iof_1.get
  // SPI1 (0 is the dedicated)
  BasePinToIOF(spi_pins(0).cs(0), iof_0(2))
  BasePinToIOF(spi_pins(0).dq(0), iof_0(3))
  BasePinToIOF(spi_pins(0).dq(1), iof_0(4))
  BasePinToIOF(spi_pins(0).sck,   iof_0(5))
  BasePinToIOF(spi_pins(0).dq(2), iof_0(6))
  BasePinToIOF(spi_pins(0).dq(3), iof_0(7))
  BasePinToIOF(spi_pins(0).cs(1), iof_0(8))
  BasePinToIOF(spi_pins(0).cs(2), iof_0(9))
  BasePinToIOF(spi_pins(0).cs(3), iof_0(10))
  // SPI2
  BasePinToIOF(spi_pins(1).cs(0), iof_0(26))
  BasePinToIOF(spi_pins(1).dq(0), iof_0(27))
  BasePinToIOF(spi_pins(1).dq(1), iof_0(28))
  BasePinToIOF(spi_pins(1).sck,   iof_0(29))
  BasePinToIOF(spi_pins(1).dq(2), iof_0(30))
  BasePinToIOF(spi_pins(1).dq(3), iof_0(31))
  // I2C
  if (sys.outer.i2cParams.length == 1) {
    BasePinToIOF(i2c_pins(0).sda, iof_0(12))
    BasePinToIOF(i2c_pins(0).scl, iof_0(13))
  }
  // UART0
  BasePinToIOF(uart_pins(0).rxd, iof_0(16))
  BasePinToIOF(uart_pins(0).txd, iof_0(17))
  // UART1
  BasePinToIOF(uart_pins(1).rxd, iof_0(24))
  BasePinToIOF(uart_pins(1).txd, iof_0(25))
  //PWM
  BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) )
  BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) )
  BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) )
  BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) )
  BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19))
  BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20))
  BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21))
  BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22))
  BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10))
  BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11))
  BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12))
  BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13))
  //-----------------------------------------------------------------------
  // Drive actual Pads
  //-----------------------------------------------------------------------
  // Result of Pin Mux
  io.pins.gpio.fromPort(sys.gpio(0))
  // Dedicated SPI Pads
  io.pins.qspi.fromPort(sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
  // JTAG Debug Interface
  val sjtag = sys.debug.systemjtag.get
  io.pins.jtag.fromPort(sjtag.jtag)
  sjtag.reset := io.jtag_reset
  sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
  io.ndreset := sys.debug.ndreset
  // AON Pads -- direct connection is OK because
  // EnhancedPin is hard-coded in MockAONPads
  // and thus there is no .fromPort method.
  io.pins.aon <> sys.aon.pins
 }
--- a/src/main/scala/everywhere/e300artydevkit/System.scala
+++ b/src/main/scala/everywhere/e300artydevkit/System.scala
@ -0,0 +1,50 @@
 // See LICENSE for license details.
 package sifive.freedom.everywhere.e300artydevkit
 import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.system._
 import sifive.blocks.devices.mockaon._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.pwm._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.i2c._
 //-------------------------------------------------------------------------
 // E300ArtyDevKitSystem
 //-------------------------------------------------------------------------
 class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketCoreplex
    with HasPeripheryMaskROMSlave
    with HasPeripheryDebug
    with HasPeripheryMockAON
    with HasPeripheryUART
    with HasPeripherySPIFlash
    with HasPeripherySPI
    with HasPeripheryGPIO
    with HasPeripheryPWM
    with HasPeripheryI2C {
  override lazy val module = new E300ArtyDevKitSystemModule(this)
 }
 class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
  extends RocketCoreplexModule(_outer)
    with HasPeripheryDebugModuleImp
    with HasPeripheryUARTModuleImp
    with HasPeripherySPIModuleImp
    with HasPeripheryGPIOModuleImp
    with HasPeripherySPIFlashModuleImp
    with HasPeripheryMockAONModuleImp
    with HasPeripheryPWMModuleImp
    with HasPeripheryI2CModuleImp {
  // Reset vector is set to the location of the mask rom
  val maskROMParams = p(PeripheryMaskROMKey)
  global_reset_vector := maskROMParams(0).address.U
 }
--- a/src/main/scala/everywhere/e300artydevkit/Top.scala
+++ b/src/main/scala/everywhere/e300artydevkit/Top.scala
@ -1,230 +0,0 @@
 // See LICENSE for license details.
 package sifive.freedom.everywhere.e300artydevkit
 import Chisel._
 import config._
 import diplomacy._
 import coreplex._
 import rocketchip._
 import uncore.devices.DebugBusIO
 import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule, GPIOPin, GPIOPinToIOF, GPIOPinIOFCtrl, GPIOInputPinCtrl, JTAGPinsIO, JTAGGPIOPort}
 import sifive.blocks.devices.mockaon.{MockAONConfig, PeripheryMockAON, PeripheryMockAONBundle, PeripheryMockAONModule, MockAONWrapperPadsIO}
 import sifive.blocks.devices.pwm.{PWMConfig, PeripheryPWM, PeripheryPWMBundle, PeripheryPWMModule, PWMGPIOPort}
 import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule, SPIFlashConfig, PeripherySPIFlash, PeripherySPIFlashBundle, PeripherySPIFlashModule, SPIPinsIO, SPIGPIOPort}
 import sifive.blocks.devices.uart.{UARTConfig, PeripheryUART, PeripheryUARTBundle, PeripheryUARTModule, UARTGPIOPort}
 import sifive.blocks.util.ResetCatchAndSync
 import util._
 // Coreplex and Periphery
 trait E300ArtyDevKitPeripheryConfigs {
  val mockAONConfig = MockAONConfig(address = 0x10000000)
  val gpioConfig = GPIOConfig(address = 0x10012000, width = 32)
  val pwmConfigs = List(
    PWMConfig(address = 0x10015000, cmpWidth = 8),
    PWMConfig(address = 0x10025000, cmpWidth = 16),
    PWMConfig(address = 0x10035000, cmpWidth = 16))
  val spiConfigs = List(
    SPIConfig(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
    SPIConfig(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
  val spiFlashConfig = SPIFlashConfig(
    fAddress = 0x20000000, rAddress = 0x10014000, sampleDelay = 3)
  val uartConfigs = List(
    UARTConfig(address = 0x10013000),
    UARTConfig(address = 0x10023000))
 }
 // This custom E300ArtyDevKit coreplex has no port into the L2 and no memory subsystem
 class E300ArtyDevKitCoreplex(implicit p: Parameters) extends BareCoreplex
    with CoreplexNetwork
    with CoreplexRISCVPlatform
    with RocketTiles {
  override lazy val module = new E300ArtyDevKitCoreplexModule(this, () => new E300ArtyDevKitCoreplexBundle(this))
 }
 class E300ArtyDevKitCoreplexBundle[+L <: E300ArtyDevKitCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
    with CoreplexNetworkBundle
    with CoreplexRISCVPlatformBundle
    with RocketTilesBundle
 class E300ArtyDevKitCoreplexModule[+L <: E300ArtyDevKitCoreplex, +B <: E300ArtyDevKitCoreplexBundle[L]](_outer: L, _io: () => B)
  extends BareCoreplexModule(_outer, _io)
    with CoreplexNetworkModule
    with CoreplexRISCVPlatformModule
    with RocketTilesModule
 class E300ArtyDevKitSystem(implicit p: Parameters) extends BaseTop
    with E300ArtyDevKitPeripheryConfigs
    with PeripheryBootROM
    with PeripheryDebug
    with PeripheryMockAON
    with PeripheryUART
    with PeripherySPIFlash
    with PeripherySPI
    with PeripheryGPIO
    with PeripheryPWM
    with HardwiredResetVector {
  override lazy val module = new E300ArtyDevKitSystemModule(this, () => new E300ArtyDevKitSystemBundle(this))
  val coreplex = LazyModule(new E300ArtyDevKitCoreplex)
  socBus.node := coreplex.mmio
  coreplex.mmioInt := intBus.intnode
 }
 class E300ArtyDevKitSystemBundle[+L <: E300ArtyDevKitSystem](_outer: L) extends BaseTopBundle(_outer)
    with E300ArtyDevKitPeripheryConfigs
    with PeripheryBootROMBundle
    with PeripheryDebugBundle
    with PeripheryUARTBundle
    with PeripherySPIBundle
    with PeripheryGPIOBundle
    with PeripherySPIFlashBundle
    with PeripheryMockAONBundle
    with PeripheryPWMBundle
    with HardwiredResetVectorBundle
 class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem, +B <: E300ArtyDevKitSystemBundle[L]](_outer: L, _io: () => B)
  extends BaseTopModule(_outer, _io)
    with E300ArtyDevKitPeripheryConfigs
    with PeripheryBootROMModule
    with PeripheryDebugModule
    with PeripheryUARTModule
    with PeripherySPIModule
    with PeripheryGPIOModule
    with PeripherySPIFlashModule
    with PeripheryMockAONModule
    with PeripheryPWMModule
    with HardwiredResetVectorModule
 // Top
 class E300ArtyDevKitTopIO(implicit val p: Parameters) extends Bundle with E300ArtyDevKitPeripheryConfigs {
  val pads = new Bundle {
    val jtag = new JTAGPinsIO
    val gpio = Vec(gpioConfig.width, new GPIOPin)
    val qspi = new SPIPinsIO(spiFlashConfig)
    val aon = new MockAONWrapperPadsIO()
  }
 }
 class E300ArtyDevKitTop(implicit val p: Parameters) extends Module with E300ArtyDevKitPeripheryConfigs {
  val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
  val io = new E300ArtyDevKitTopIO
  // This needs to be de-asserted synchronously to the coreClk.
  val async_corerst = sys.io.aon.rsts.corerst
  sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
  // ------------------------------------------------------------
  // Check for unsupported RCT Connections
  // ------------------------------------------------------------
  require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
  // ------------------------------------------------------------
  // Build GPIO Pin Mux
  // ------------------------------------------------------------
  // Pin Mux for UART, SPI, PWM
  // First convert the System outputs into "IOF" using the respective *GPIOPort
  // converters.
  val sys_uarts = sys.io.uarts
  val sys_pwms  = sys.io.pwms
  val sys_spis   = sys.io.spis
  val uart_pins = uartConfigs.map { c => Module (new UARTGPIOPort) }
  val pwm_pins  = pwmConfigs.map  { c => Module (new PWMGPIOPort(c.bc)) }
  val spi_pins  = spiConfigs.map  { c => Module (new SPIGPIOPort(c)) }
  (uart_pins zip sys_uarts) map {case (p, r) => p.io.uart <> r}
  (pwm_pins zip  sys_pwms)  map {case (p, r) => p.io.pwm  <> r}
  (spi_pins zip  sys_spis)  map {case (p, r) => p.io.spi <> r}
  // ------------------------------------------------------------
  // Default Pin connections before attaching pinmux
  for (iof_0 <- sys.io.gpio.iof_0) {
    iof_0.o := GPIOPinIOFCtrl()
  }
  for (iof_1 <- sys.io.gpio.iof_1) {
    iof_1.o := GPIOPinIOFCtrl()
  }
  // ------------------------------------------------------------
  // TODO: Make this mapping more programmatic.
  val iof_0 = sys.io.gpio.iof_0
  val iof_1 = sys.io.gpio.iof_1
  // SPI1 (0 is the dedicated)
  GPIOPinToIOF(spi_pins(0).io.pins.cs(0), iof_0(2))
  GPIOPinToIOF(spi_pins(0).io.pins.dq(0), iof_0(3))
  GPIOPinToIOF(spi_pins(0).io.pins.dq(1), iof_0(4))
  GPIOPinToIOF(spi_pins(0).io.pins.sck,   iof_0(5))
  GPIOPinToIOF(spi_pins(0).io.pins.dq(2), iof_0(6))
  GPIOPinToIOF(spi_pins(0).io.pins.dq(3), iof_0(7))
  GPIOPinToIOF(spi_pins(0).io.pins.cs(1), iof_0(8))
  GPIOPinToIOF(spi_pins(0).io.pins.cs(2), iof_0(9))
  GPIOPinToIOF(spi_pins(0).io.pins.cs(3), iof_0(10))
  // SPI2
  GPIOPinToIOF(spi_pins(1).io.pins.cs(0), iof_0(26))
  GPIOPinToIOF(spi_pins(1).io.pins.dq(0), iof_0(27))
  GPIOPinToIOF(spi_pins(1).io.pins.dq(1), iof_0(28))
  GPIOPinToIOF(spi_pins(1).io.pins.sck,   iof_0(29))
  GPIOPinToIOF(spi_pins(1).io.pins.dq(2), iof_0(30))
  GPIOPinToIOF(spi_pins(1).io.pins.dq(3), iof_0(31))
  // UART0
  GPIOPinToIOF(uart_pins(0).io.pins.rxd, iof_0(16))
  GPIOPinToIOF(uart_pins(0).io.pins.txd, iof_0(17))
  // UART1
  GPIOPinToIOF(uart_pins(1).io.pins.rxd, iof_0(24))
  GPIOPinToIOF(uart_pins(1).io.pins.txd, iof_0(25))
  //PWM
  GPIOPinToIOF(pwm_pins(0).io.pins.pwm(0), iof_1(0) )
  GPIOPinToIOF(pwm_pins(0).io.pins.pwm(1), iof_1(1) )
  GPIOPinToIOF(pwm_pins(0).io.pins.pwm(2), iof_1(2) )
  GPIOPinToIOF(pwm_pins(0).io.pins.pwm(3), iof_1(3) )
  GPIOPinToIOF(pwm_pins(1).io.pins.pwm(1), iof_1(19))
  GPIOPinToIOF(pwm_pins(1).io.pins.pwm(0), iof_1(20))
  GPIOPinToIOF(pwm_pins(1).io.pins.pwm(2), iof_1(21))
  GPIOPinToIOF(pwm_pins(1).io.pins.pwm(3), iof_1(22))
  GPIOPinToIOF(pwm_pins(2).io.pins.pwm(0), iof_1(10))
  GPIOPinToIOF(pwm_pins(2).io.pins.pwm(1), iof_1(11))
  GPIOPinToIOF(pwm_pins(2).io.pins.pwm(2), iof_1(12))
  GPIOPinToIOF(pwm_pins(2).io.pins.pwm(3), iof_1(13))
  // ------------------------------------------------------------
  // Drive actual Pads
  // ------------------------------------------------------------
  // Result of Pin Mux
  io.pads.gpio <> sys.io.gpio.pins
  val dedicated_spi_pins = Module (new SPIGPIOPort(spiFlashConfig, syncStages=3, driveStrength=Bool(true)))
  dedicated_spi_pins.clock := sys.clock
  dedicated_spi_pins.reset := sys.reset
  io.pads.qspi <> dedicated_spi_pins.io.pins
  dedicated_spi_pins.io.spi <> sys.io.qspi
  // JTAG Debug Interface
  val jtag_pins = Module (new JTAGGPIOPort(true))
  io.pads.jtag <> jtag_pins.io.pins
  sys.io.jtag.get <> jtag_pins.io.jtag
  // Override TRST to reset this logic IFF the core is in reset.
  // This will require 3 ticks of TCK before the debug logic
  // comes out of reset, but JTAG needs 5 ticks anyway.
  // This means that the "real" TRST is never actually used in this design.
  sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, async_corerst)
  // AON Pads
  io.pads.aon <> sys.io.aon.pads
 }
--- a/src/main/scala/unleashed/u500vc707devkit/Config.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/Config.scala
@ -0,0 +1,52 @@
 // See LICENSE for license details.
 package sifive.freedom.unleashed.u500vc707devkit
 import freechips.rocketchip.config._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 // Default FreedomUVC707Config
 class FreedomUVC707Config extends Config(
  new WithJtagDTM            ++
  new WithNMemoryChannels(1) ++
  new WithNBigCores(1)       ++
  new BaseConfig
 )
 // Freedom U500 VC707 Dev Kit Peripherals
 class U500VC707DevKitPeripherals extends Config((site, here, up) => {
  case PeripheryUARTKey => List(
    UARTParams(address = BigInt(0x54000000L)))
  case PeripherySPIKey => List(
    SPIParams(rAddress = BigInt(0x54001000L)))
  case PeripheryGPIOKey => List(
    GPIOParams(address = BigInt(0x54002000L), width = 4))
  case PeripheryMaskROMKey => List(
    MaskROMParams(address = 0x10000, name = "BootROM"))
 })
 // Freedom U500 VC707 Dev Kit
 class U500VC707DevKitConfig extends Config(
  new WithoutFPU                 ++
  new WithNExtTopInterrupts(0)   ++
  new U500VC707DevKitPeripherals ++
  new FreedomUVC707Config().alter((site,here,up) => {
    case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
    case PeripheryBusParams => up(PeripheryBusParams, site).copy(frequency = 50000000) // 50 MHz hperiphery
    case DTSTimebase => BigInt(1000000)
    case ExtMem => up(ExtMem).copy(size = 0x40000000L)
    case JtagDTMKey => new JtagDTMConfig (
      idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
      idcodePartNum = 0x000,  // Decided to simplify.
      idcodeManufId = 0x489,  // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
      debugIdleCycles = 5)    // Reasonable guess for synchronization
  })
 )
--- a/src/main/scala/unleashed/u500vc707devkit/Configs.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/Configs.scala
@ -1,28 +0,0 @@
 // See LICENSE for license details.
 package sifive.freedom.unleashed.u500vc707devkit
 import config._
 import coreplex.{WithL1DCacheWays, WithSmallCores, WithoutFPU, BootROMFile}
 import rocketchip.{BaseConfig,WithRTCPeriod,WithJtagDTM}
 // Don't use directly. Requires additional bootfile configuration
 class DefaultFreedomUConfig extends Config(
  new WithJtagDTM ++ new BaseConfig
 )
 class WithBootROMFile(bootROMFile: String) extends Config(
  (pname, site, here) => pname match {
    case BootROMFile => bootROMFile
    case _ => throw new CDEMatchError
  }
 )
 //----------------------------------------------------------------------------------
 // Freedom U500 VC707 Dev Kit
 class U500VC707DevKitConfig extends Config(
  new WithBootROMFile("./bootrom/u500vc707devkit.img") ++
  new WithRTCPeriod(62) ++    //Default value of 100 generates 1 Mhz clock @ 100Mhz, then corrected in sbi_entry.c
                              //Value 62 generates ~ 1Mhz clock @ 62.5Mhz
  new WithoutFPU ++
  new DefaultFreedomUConfig)
--- a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala
@ -0,0 +1,69 @@
 // See LICENSE for license details.
 package sifive.freedom.unleashed.u500vc707devkit
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.pinctrl.{BasePin}
 import sifive.fpgashells.shell.xilinx.vc707shell.{VC707Shell}
 import sifive.fpgashells.ip.xilinx.{IOBUF}
 //-------------------------------------------------------------------------
 // PinGen
 //-------------------------------------------------------------------------
 object PinGen {
  def apply(): BasePin = {
    new BasePin()
  }
 }
 //-------------------------------------------------------------------------
 // U500VC707DevKitFPGAChip
 //-------------------------------------------------------------------------
 class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707Shell {
  //-----------------------------------------------------------------------
  // DUT
  //-----------------------------------------------------------------------
  // Connect the clock to the 50 Mhz output from the PLL
  dut_clock := clk50
  withClockAndReset(dut_clock, dut_reset) {
    val dut = Module(LazyModule(new U500VC707DevKitSystem).module)
    //---------------------------------------------------------------------
    // Connect peripherals
    //---------------------------------------------------------------------
    connectDebugJTAG(dut)
    connectSPI      (dut)
    connectUART     (dut)
    connectPCIe     (dut)
    connectMIG      (dut)
    //---------------------------------------------------------------------
    // GPIO
    //---------------------------------------------------------------------
    val gpioParams = p(PeripheryGPIOKey)
    val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
    gpio_pins.fromPort(dut.gpio(0))
    gpio_pins.pins.foreach { _.i.ival := Bool(false) }
    gpio_pins.pins.zipWithIndex.foreach {
      case(pin, idx) => led(idx) := pin.o.oval
    }
    // tie to zero
    for( idx <- 7 to 4 ) { led(idx) := false.B }
  }
 }
--- a/src/main/scala/unleashed/u500vc707devkit/System.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/System.scala
@ -0,0 +1,48 @@
 // See LICENSE for license details.
 package sifive.freedom.unleashed.u500vc707devkit
 import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.system._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
 //-------------------------------------------------------------------------
 // U500VC707DevKitSystem
 //-------------------------------------------------------------------------
 class U500VC707DevKitSystem(implicit p: Parameters) extends RocketCoreplex
    with HasPeripheryMaskROMSlave
    with HasPeripheryDebug
    with HasSystemErrorSlave
    with HasPeripheryUART
    with HasPeripherySPI
    with HasPeripheryGPIO
    with HasMemoryXilinxVC707MIG
    with HasSystemXilinxVC707PCIeX1 {
  override lazy val module = new U500VC707DevKitSystemModule(this)
 }
 class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem](_outer: L)
  extends RocketCoreplexModule(_outer)
    with HasRTCModuleImp
    with HasPeripheryDebugModuleImp
    with HasPeripheryUARTModuleImp
    with HasPeripherySPIModuleImp
    with HasPeripheryGPIOModuleImp
    with HasMemoryXilinxVC707MIGModuleImp
    with HasSystemXilinxVC707PCIeX1ModuleImp {
  // Reset vector is set to the location of the mask rom
  val maskROMParams = p(PeripheryMaskROMKey)
  global_reset_vector := maskROMParams(0).address.U
 }
--- a/src/main/scala/unleashed/u500vc707devkit/Top.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/Top.scala
@ -1,299 +0,0 @@
 // See LICENSE for license details.
 package sifive.freedom.unleashed.u500vc707devkit
 import Chisel._
 import config._
 import util._
 import junctions._
 import diplomacy._
 import uncore.tilelink._
 import uncore.devices._
 import uncore.util._
 import uncore.converters._
 import rocket._
 import coreplex._
 import rocketchip._
 import sifive.blocks.devices.xilinxvc707mig._
 import sifive.blocks.devices.xilinxvc707pciex1._
 import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule}
 import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule}
 import sifive.blocks.devices.uart._
 import sifive.blocks.util.ResetCatchAndSync
 trait PeripheryConfigs {
  val uartConfigs = List(UARTConfig(address = BigInt(0x54000000L)))
  val spiConfigs = List(SPIConfig(rAddress = BigInt(0x54001000L)))
  val gpioConfig = GPIOConfig(address = BigInt(0x54002000L), width = 4)
 }
 class U500VC707DevKitSystem(implicit p: Parameters) extends BaseTop
    with PeripheryConfigs
    with PeripheryBootROM
    with PeripheryDebug
    with PeripheryCounter
    with PeripheryUART
    with PeripherySPI
    with PeripheryGPIO
    with PeripheryXilinxVC707MIG
    with PeripheryXilinxVC707PCIeX1
    with HardwiredResetVector
    with RocketPlexMaster {
  override lazy val module = new U500VC707DevKitSystemModule(this, () => new U500VC707DevKitSystemBundle(this))
  // scalastyle:off method.length
  ConfigStringOutput.contents = Some {
    """platform {
      |  vendor ucb;
      |  arch spike;
      |};
      |plic {
      |  interface "plic";
      |  ndevs 9;
      |  priority { mem { 0x0c000000 0x0c00ffff; }; };
      |  pending  { mem { 0x0c001000 0x0c00107f; }; };
      |  0 {
      |    0 {
      |      m {
      |        ie  { mem { 0x0c002000 0x0c00207f; }; };
      |        ctl { mem { 0x0c200000 0x0c200007; }; };
      |      };
      |      s {
      |        ie  { mem { 0x0c002080 0x0c0020ff; }; };
      |        ctl { mem { 0x0c201000 0x0c201007; }; };
      |      };
      |  };
      |  };
      |};
      |pcie {
      |  interface "xilinx-pcie-rv";
      |  bus {
      |    mem { 0x60000000 0x7fffffff; } { 0x200000000 0x3ffffffff; };
      |    bus { 1 63; };
      |  };
      |  bridge {
      |    mem { 0x50000000 0x53ffffff; };
      |    bus 0;
      |    irq 6;
      |  };
      |};
      |leds {
      |  interface "gpio";
      |  ngpio 4;
      |  mem { 0x54002000 0x54002003; };
      |};
      |rtc {
      |  addr 0x200bff8;
      |};
      |ram {
      |  0 {
      |    addr 0x80000000;
      |    size 0x10000000;
      |  };
      |};
      |uart {
      |  addr 0x54000000;
      |};
      |core {
      |  0 {
      |    0 {
      |      isa rv64ima;
      |      timecmp 0x02004000;
      |      ipi 0x02000000;
      |    };
      |  };
      |};
      |\u0000""".stripMargin
  }
  // scalastyle:on method.length
 }
 class U500VC707DevKitSystemBundle[+L <: U500VC707DevKitSystem](_outer: L) extends BaseTopBundle(_outer)
    with PeripheryConfigs
    with PeripheryBootROMBundle
    with PeripheryDebugBundle
    with PeripheryCounterBundle
    with PeripheryUARTBundle
    with PeripherySPIBundle
    with PeripheryGPIOBundle
    with PeripheryXilinxVC707MIGBundle
    with PeripheryXilinxVC707PCIeX1Bundle
    with HardwiredResetVectorBundle
    with RocketPlexMasterBundle
 class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem, +B <: U500VC707DevKitSystemBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
    with PeripheryConfigs
    with PeripheryBootROMModule
    with PeripheryDebugModule
    with PeripheryCounterModule
    with PeripheryUARTModule
    with PeripherySPIModule
    with PeripheryGPIOModule
    with PeripheryXilinxVC707MIGModule
    with PeripheryXilinxVC707PCIeX1Module
    with HardwiredResetVectorModule
    with RocketPlexMasterModule
 /////
 class ResetDone extends Module {
  //unused - in future io.resetdone can set rocketchip STOP_COND/PRINTF_COND
  val io = new Bundle{
    val reset = Bool(INPUT)
    val resetdone = Bool(OUTPUT)
  }
  val resetdonereg = Reg(init = Bool(false))
  val resetff = Reg(init = Bool(false))
  resetff := io.reset;
  resetdonereg := Mux( ((!io.reset)&&resetff), UInt("b1"), resetdonereg)
  io.resetdone := resetdonereg
 }
 /////
 class U500VC707DevKitIO(implicit val p: Parameters) extends Bundle
    with PeripheryConfigs
    with PeripheryUARTBundle
    with PeripherySPIBundle
    with PeripheryGPIOBundle
 {
  val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
  val jtag = p(IncludeJtagDTM).option(new JTAGIO(true).flip)
  //MIG
  val xilinxvc707mig = new XilinxVC707MIGPads
  //PCIe
  val xilinxvc707pcie = new XilinxVC707PCIeX1Pads
  //Clocks
  val sys_clk_n = Bool(INPUT)
  val sys_clk_p = Bool(INPUT)
  val pcie_refclk_p = Bool(INPUT)
  val pcie_refclk_n = Bool(INPUT)
  //Reset
  val sys_reset = Bool(INPUT)
  //Misc outputs used in system.v
  val core_reset = Bool(OUTPUT)
  val core_clock = Clock(OUTPUT)
 }
 /////
 class U500VC707DevKitTop(implicit val p: Parameters) extends Module {
  // ------------------------------------------------------------
  // Instantiate U500 VC707 Dev Kit system (sys)
  // ------------------------------------------------------------
  val sys = Module(LazyModule(new U500VC707DevKitSystem).module)
  val io = new U500VC707DevKitIO
  // ------------------------------------------------------------
  // Clock and Reset
  // ------------------------------------------------------------
  val mig_mmcm_locked     = Wire(Bool())
  val mig_sys_reset       = Wire(Bool())
  val init_calib_complete = Wire(Bool())
  val mmcm_lock_pcie      = Wire(Bool())
  val do_reset            = Wire(Bool())
  val mig_clock           = Wire(Clock())
  val mig_resetn          = Wire(Bool())
  val top_resetn          = Wire(Bool())
  val pcie_dat_reset      = Wire(Bool())
  val pcie_dat_resetn     = Wire(Bool())
  val pcie_cfg_reset      = Wire(Bool())
  val pcie_cfg_resetn     = Wire(Bool())
  val pcie_dat_clock      = Wire(Clock())
  val pcie_cfg_clock      = Wire(Clock())
  val top_clock           = Wire(Clock())
  val top_reset           = Wire(Bool())
  val mig_reset           = Wire(Bool())
  do_reset             := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset
  mig_resetn           := !mig_reset
  top_resetn           := !top_reset
  pcie_dat_resetn      := !pcie_dat_reset
  pcie_cfg_resetn      := !pcie_cfg_reset
  // For now, run the CPU synchronous to the PCIe data bus
  top_clock            := pcie_dat_clock
  val safe_reset = Module(new vc707reset)
  safe_reset.io.areset := do_reset
  safe_reset.io.clock1 := mig_clock
  mig_reset            := safe_reset.io.reset1
  safe_reset.io.clock2 := pcie_dat_clock
  pcie_dat_reset       := safe_reset.io.reset2
  safe_reset.io.clock3 := pcie_cfg_clock
  pcie_cfg_reset       := safe_reset.io.reset3
  safe_reset.io.clock4 := top_clock
  top_reset            := safe_reset.io.reset4
  sys.clock := top_clock
  sys.reset := top_reset
  // ------------------------------------------------------------
  // UART
  // ------------------------------------------------------------
  io.uarts <> sys.io.uarts
  // ------------------------------------------------------------
  // SPI
  // ------------------------------------------------------------
  io.spis <> sys.io.spis
  // ------------------------------------------------------------
  // GPIO
  // ------------------------------------------------------------
  io.gpio <> sys.io.gpio
  // ------------------------------------------------------------
  // MIG
  // ------------------------------------------------------------
  sys.io.xilinxvc707mig.sys_clk_p := io.sys_clk_p
  sys.io.xilinxvc707mig.sys_clk_n := io.sys_clk_n
  mig_clock                              := sys.io.xilinxvc707mig.ui_clk
  mig_sys_reset                          := sys.io.xilinxvc707mig.ui_clk_sync_rst
  mig_mmcm_locked                        := sys.io.xilinxvc707mig.mmcm_locked
  sys.io.xilinxvc707mig.aresetn   := mig_resetn
  init_calib_complete                    := sys.io.xilinxvc707mig.init_calib_complete
  sys.io.xilinxvc707mig.sys_rst   := io.sys_reset
  //the below bundle assignment is dangerous and relies on matching signal names
  //  io.xilinxvc707 is of type XilinxVC707MIGPads
  //  sys.io.xilinxvc707mig is of type XilinxVC707MIGIO
  io.xilinxvc707mig <> sys.io.xilinxvc707mig
  // ------------------------------------------------------------
  // PCIe
  // ------------------------------------------------------------
  sys.io.xilinxvc707pcie.axi_aresetn      := pcie_dat_resetn
  pcie_dat_clock                                 := sys.io.xilinxvc707pcie.axi_aclk_out
  pcie_cfg_clock                                 := sys.io.xilinxvc707pcie.axi_ctl_aclk_out
  mmcm_lock_pcie                                 := sys.io.xilinxvc707pcie.mmcm_lock
  sys.io.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
  sys.io.xilinxvc707pcie.REFCLK_rxp      := io.pcie_refclk_p
  sys.io.xilinxvc707pcie.REFCLK_rxn      := io.pcie_refclk_n
  //another dangerous bundle assignment which relies on matching signal names
  //  io.xilinxvc707pcie is of type XilinxVC707PCIeX1Pads
  //  sys.io.xilinxvc707pcie is of type XilinxVC707PCIeX1IO
  io.xilinxvc707pcie <> sys.io.xilinxvc707pcie
  // ------------------------------------------------------------
  // Debug
  // ------------------------------------------------------------
  if (p(IncludeJtagDTM)) {
    sys.io.jtag.get <> io.jtag.get
    //Override TRST to reset this logic IFF the core is in reset.
    // This will require 3 ticks of TCK before the debug logic
    // comes out of reset, but JTAG needs 5 ticks anyway.
    // This means that the "real" TRST is never actually used.
    sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, top_reset)
  }else{
    // SimDTM; only for simulation use
    sys.io.debug.get := io.debug.get
    // test_mode_clk shouldn't be used for simulation
    //sys.io.test_mode_clk := Bool(false).asClock
  }
  // ------------------------------------------------------------
  // Misc outputs used in system.v
  // ------------------------------------------------------------
  io.core_clock := top_clock
  io.core_reset := top_reset
 }
--- a/src/main/scala/unleashed/u500vc707devkit/vc707reset.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/vc707reset.scala
@ -1,22 +0,0 @@
 // See LICENSE for license details.
 package sifive.freedom.unleashed.u500vc707devkit
 import Chisel._
 //scalastyle:off
 //turn off linter: blackbox name must match verilog module 
 class vc707reset() extends BlackBox
 {
  val io = new Bundle{
    val areset = Bool(INPUT)
    val clock1 = Clock(INPUT)
    val reset1 = Bool(OUTPUT)
    val clock2 = Clock(INPUT)
    val reset2 = Bool(OUTPUT)
    val clock3 = Clock(INPUT)
    val reset3 = Bool(OUTPUT)
    val clock4 = Clock(INPUT)
    val reset4 = Bool(OUTPUT)
  }
 }
 //scalastyle:on
		`@ -0,0 +1 @@`
							`Subproject commit 2389e6e95717caca782e7444422da16fef687188`
		`@ -1 +1 @@`
			`Subproject commit 4146f6a792277297bd80d4b6f1b6f2b3cb0f31d7`				`Subproject commit 82df766f4a5b1efb24b8659eb11c8b12c410a291`
		`@ -1 +1 @@`
			`Subproject commit 7916ef5249c72a3a84c599d123760f4d716de58a`				`Subproject commit f266b55da92e42350be5704b4fe7d2a934e986ae`