Updates to Freedom SoCs
This commit is contained in:
Shreesha Srinath
committed by
Yunsup Lee
Yunsup Lee
parent
f4375c2266
commit
ec70d85cbc
177
src/main/scala/everywhere/e300artydevkit/Platform.scala
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177
src/main/scala/everywhere/e300artydevkit/Platform.scala
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.system._
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import sifive.blocks.util.{ResetCatchAndSync}
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import sifive.blocks.devices.mockaon._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.jtag._
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import sifive.blocks.devices.pwm._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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import sifive.blocks.devices.pinctrl._
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//-------------------------------------------------------------------------
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// PinGen
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//-------------------------------------------------------------------------
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object PinGen {
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def apply(): BasePin = {
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val pin = new BasePin()
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pin
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}
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}
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//-------------------------------------------------------------------------
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// E300ArtyDevKitPlatformIO
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//-------------------------------------------------------------------------
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class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
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val pins = new Bundle {
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val jtag = new JTAGPins(() => PinGen(), false)
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val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))
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val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))
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val aon = new MockAONWrapperPins()
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}
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val jtag_reset = Bool(INPUT)
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val ndreset = Bool(OUTPUT)
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}
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//-------------------------------------------------------------------------
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// E300ArtyDevKitPlatform
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//-------------------------------------------------------------------------
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class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
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val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
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val io = new E300ArtyDevKitPlatformIO
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// This needs to be de-asserted synchronously to the coreClk.
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val async_corerst = sys.aon.rsts.corerst
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// Add in debug-controlled reset.
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sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
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//-----------------------------------------------------------------------
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// Check for unsupported rocket-chip connections
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//-----------------------------------------------------------------------
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require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
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//-----------------------------------------------------------------------
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// Build GPIO Pin Mux
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//-----------------------------------------------------------------------
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// Pin Mux for UART, SPI, PWM
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// First convert the System outputs into "IOF" using the respective *GPIOPort
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// converters.
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val sys_uart = sys.uart
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val sys_pwm = sys.pwm
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val sys_spi = sys.spi
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val sys_i2c = sys.i2c
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val uart_pins = sys.outer.uartParams.map { c => Wire(new UARTPins(() => PinGen()))}
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val pwm_pins = sys.outer.pwmParams.map { c => Wire(new PWMPins(() => PinGen(), c))}
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val spi_pins = sys.outer.spiParams.map { c => Wire(new SPIPins(() => PinGen(), c))}
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val i2c_pins = sys.outer.i2cParams.map { c => Wire(new I2CPins(() => PinGen()))}
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(uart_pins zip sys_uart) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
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(pwm_pins zip sys_pwm) map {case (p, r) => p.fromPort(r)}
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(spi_pins zip sys_spi) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
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(i2c_pins zip sys_i2c) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
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//-----------------------------------------------------------------------
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// Default Pin connections before attaching pinmux
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for (iof_0 <- sys.gpio(0).iof_0.get) {
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iof_0.default()
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}
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for (iof_1 <- sys.gpio(0).iof_1.get) {
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iof_1.default()
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}
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//-----------------------------------------------------------------------
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val iof_0 = sys.gpio(0).iof_0.get
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val iof_1 = sys.gpio(0).iof_1.get
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// SPI1 (0 is the dedicated)
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BasePinToIOF(spi_pins(0).cs(0), iof_0(2))
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BasePinToIOF(spi_pins(0).dq(0), iof_0(3))
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BasePinToIOF(spi_pins(0).dq(1), iof_0(4))
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BasePinToIOF(spi_pins(0).sck, iof_0(5))
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BasePinToIOF(spi_pins(0).dq(2), iof_0(6))
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BasePinToIOF(spi_pins(0).dq(3), iof_0(7))
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BasePinToIOF(spi_pins(0).cs(1), iof_0(8))
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BasePinToIOF(spi_pins(0).cs(2), iof_0(9))
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BasePinToIOF(spi_pins(0).cs(3), iof_0(10))
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// SPI2
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BasePinToIOF(spi_pins(1).cs(0), iof_0(26))
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BasePinToIOF(spi_pins(1).dq(0), iof_0(27))
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BasePinToIOF(spi_pins(1).dq(1), iof_0(28))
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BasePinToIOF(spi_pins(1).sck, iof_0(29))
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BasePinToIOF(spi_pins(1).dq(2), iof_0(30))
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BasePinToIOF(spi_pins(1).dq(3), iof_0(31))
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// I2C
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if (sys.outer.i2cParams.length == 1) {
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BasePinToIOF(i2c_pins(0).sda, iof_0(12))
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BasePinToIOF(i2c_pins(0).scl, iof_0(13))
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}
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// UART0
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BasePinToIOF(uart_pins(0).rxd, iof_0(16))
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BasePinToIOF(uart_pins(0).txd, iof_0(17))
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// UART1
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BasePinToIOF(uart_pins(1).rxd, iof_0(24))
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BasePinToIOF(uart_pins(1).txd, iof_0(25))
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//PWM
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BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) )
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BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) )
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BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) )
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BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) )
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BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19))
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BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20))
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BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21))
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BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22))
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BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10))
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BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11))
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BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12))
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BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13))
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//-----------------------------------------------------------------------
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// Drive actual Pads
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//-----------------------------------------------------------------------
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// Result of Pin Mux
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io.pins.gpio.fromPort(sys.gpio(0))
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// Dedicated SPI Pads
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io.pins.qspi.fromPort(sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
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// JTAG Debug Interface
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val sjtag = sys.debug.systemjtag.get
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io.pins.jtag.fromPort(sjtag.jtag)
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sjtag.reset := io.jtag_reset
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sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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io.ndreset := sys.debug.ndreset
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// AON Pads -- direct connection is OK because
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// EnhancedPin is hard-coded in MockAONPads
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// and thus there is no .fromPort method.
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io.pins.aon <> sys.aon.pins
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}
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