riscv/freedom
1
0
Fork 0
Code Issues Releases Activity

Updates to Freedom SoCs

Browse Source
This commit is contained in:
Shreesha Srinath
2017-08-18 18:21:04 -07:00
committed by Yunsup Lee
parent f4375c2266
commit ec70d85cbc
64 changed files with 1713 additions and 3449 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
Makefile.e300artydevkit
View File

@ -1,17 +1,22 @@
# See LICENSE for license details.
base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
BUILD_DIR := $(base_dir)/builds/e300artydevkit
FPGA_DIR := $(base_dir)/fpga/e300artydevkit
MODEL := E300ArtyDevKitTop
FPGA_DIR := $(base_dir)/fpga-shells/xilinx
MODEL := E300ArtyDevKitFPGAChip
PROJECT := sifive.freedom.everywhere.e300artydevkit
CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
CONFIG := E300ArtyDevKitConfig
export CONFIG := E300ArtyDevKitConfig
export BOARD := arty
export BOOTROM_DIR := $(base_dir)/bootrom/xip
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
EXTRA_FPGA_VSRCS := \
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
include common.mk