diff --git a/src/main/scala/unleashed/u500ml507devkit/Config.scala b/src/main/scala/unleashed/u500ml507devkit/Config.scala
index 4d65d2a..e88d64b 100644
--- a/src/main/scala/unleashed/u500ml507devkit/Config.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/Config.scala
@@ -13,7 +13,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 
-import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams}
+import sifive.freedom.unleashed.u500ml507devkit.fpga._
 
 // Default FreedomUML507Config
 class FreedomUML507Config extends Config(
@@ -42,7 +42,7 @@ class U500ML507DevKitConfig extends Config(
   new FreedomUML507Config().alter((site,here,up) => {
     case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
     case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
-    case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
+    case MemoryML507Key => MemoryML507Params(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
     case DTSTimebase => BigInt(1000000)
     case ExtMem => up(ExtMem).copy(size = 0x40000000L)
     case JtagDTMKey => new JtagDTMConfig (
diff --git a/src/main/scala/unleashed/u500ml507devkit/System.scala b/src/main/scala/unleashed/u500ml507devkit/System.scala
index 7a47b39..bc25138 100644
--- a/src/main/scala/unleashed/u500ml507devkit/System.scala
+++ b/src/main/scala/unleashed/u500ml507devkit/System.scala
@@ -14,6 +14,8 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 
+import sifive.freedom.unleashed.u500ml507devkit.fpga._
+
 //-------------------------------------------------------------------------
 // U500ML507DevKitSystem
 //-------------------------------------------------------------------------
@@ -24,7 +26,8 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
     with HasSystemErrorSlave
     with HasPeripheryUART
     with HasPeripherySPI
-    with HasPeripheryGPIO {
+    with HasPeripheryGPIO
+    with HasMemoryML507 {
   override lazy val module = new U500ML507DevKitSystemModule(this)
 }
 
diff --git a/src/main/scala/unleashed/u500ml507devkit/fpga/Memory.scala b/src/main/scala/unleashed/u500ml507devkit/fpga/Memory.scala
new file mode 100644
index 0000000..dd51758
--- /dev/null
+++ b/src/main/scala/unleashed/u500ml507devkit/fpga/Memory.scala
@@ -0,0 +1,55 @@
+// See LICENSE.SiFive for license details.
+
+package sifive.freedom.unleashed.u500ml507devkit.fpga
+
+import Chisel._
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
+case class MemoryML507Params(
+    address: Seq[AddressSet]
+)
+
+case object MemoryML507Key extends Field[MemoryML507Params]
+
+trait HasMemoryML507 { this: BaseSubsystem =>
+    val memory = LazyModule(new TLMemoryML507(p(MemoryML507Key)))
+
+    // TODO: right TL/memory node chain?
+    memory.node := memBuses.head.toDRAMController(Some("ml507mig"))()
+}
+
+class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyModule {
+    val width = 512
+    val beatBytes = width/8 // TODO: To wide? TLFragmenter? fixedSize?
+
+    val device = new MemoryDevice
+    val node = TLManagerNode(
+        Seq(TLManagerPortParameters(
+            Seq(TLManagerParameters(
+                address         = c.address,
+                resources       = device.reg,
+                regionType      = RegionType.UNCACHED,
+                executable      = true,
+                supportsGet     = TransferSizes(1, beatBytes),
+                supportsPutFull = TransferSizes(1, beatBytes),
+                fifoId          = Some(0) // in-order
+            )),
+            beatBytes = beatBytes
+        ))
+    )
+
+    lazy val module = new LazyModuleImp(this) {
+        val (in, edge)= node.in(0)
+
+        // Tie off unused channels
+        in.a.ready := Bool(true)
+        in.b.valid := Bool(false)
+        in.c.ready := Bool(true)
+        in.d.valid := Bool(false)
+        in.e.ready := Bool(true)
+    }
+}