From 756e2e82a105fe01782f090f52ebf3b98af39e39 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 25 Feb 2018 10:33:25 -0800 Subject: [PATCH] build: update all submodules to their current master --- Makefile.e300artydevkit | 2 +- Makefile.u500vc707devkit | 2 +- bootrom/sdboot/Makefile | 4 ++-- bootrom/xip/Makefile | 4 ++-- common.mk | 2 +- fpga-shells | 2 +- rocket-chip | 2 +- sifive-blocks | 2 +- src/main/scala/unleashed/u500vc707devkit/Config.scala | 8 ++++---- src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala | 3 ++- 10 files changed, 16 insertions(+), 15 deletions(-) diff --git a/Makefile.e300artydevkit b/Makefile.e300artydevkit index 04b0af5..b776752 100644 --- a/Makefile.e300artydevkit +++ b/Makefile.e300artydevkit @@ -4,7 +4,7 @@ BUILD_DIR := $(base_dir)/builds/e300artydevkit FPGA_DIR := $(base_dir)/fpga-shells/xilinx MODEL := E300ArtyDevKitFPGAChip PROJECT := sifive.freedom.everywhere.e300artydevkit -CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit +export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit export CONFIG := E300ArtyDevKitConfig export BOARD := arty export BOOTROM_DIR := $(base_dir)/bootrom/xip diff --git a/Makefile.u500vc707devkit b/Makefile.u500vc707devkit index 70692fa..b22179a 100644 --- a/Makefile.u500vc707devkit +++ b/Makefile.u500vc707devkit @@ -4,7 +4,7 @@ BUILD_DIR := $(base_dir)/builds/u500vc707devkit FPGA_DIR := $(base_dir)/fpga-shells/xilinx MODEL := U500VC707DevKitFPGAChip PROJECT := sifive.freedom.unleashed.u500vc707devkit -CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit +export CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit export CONFIG := U500VC707DevKitConfig export BOARD := vc707 export BOOTROM_DIR := $(base_dir)/bootrom/sdboot diff --git a/bootrom/sdboot/Makefile b/bootrom/sdboot/Makefile index e4bb3d1..571b455 100644 --- a/bootrom/sdboot/Makefile +++ b/bootrom/sdboot/Makefile @@ -7,8 +7,8 @@ CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0 CFLAGS+= -I $(BOOTROM_DIR)/include -I. LFLAGS=-static -nostdlib -L $(BOOTROM_DIR)/linker -T sdboot.elf.lds -dtb := $(BUILD_DIR)/$(CONFIG).dtb -$(dtb): $(BUILD_DIR)/$(CONFIG).dts +dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb +$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts dtc -I dts -O dtb -o $@ $< .PHONY: dtb diff --git a/bootrom/xip/Makefile b/bootrom/xip/Makefile index 08753ce..57f94d4 100644 --- a/bootrom/xip/Makefile +++ b/bootrom/xip/Makefile @@ -5,8 +5,8 @@ OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g LFLAGS=-static -nostdlib -dtb := $(BUILD_DIR)/$(CONFIG).dtb -$(dtb): $(BUILD_DIR)/$(CONFIG).dts +dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb +$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts dtc -I dts -O dtb -o $@ $< .PHONY: dtb diff --git a/common.mk b/common.mk index e23cbb7..1a1407a 100644 --- a/common.mk +++ b/common.mk @@ -46,7 +46,7 @@ $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.sc firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR) mkdir -p $(dir $@) - $(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)" + $(SBT) "runMain freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)" .PHONY: firrtl firrtl: $(firrtl) diff --git a/fpga-shells b/fpga-shells index ba7beb6..17e13a3 160000 --- a/fpga-shells +++ b/fpga-shells @@ -1 +1 @@ -Subproject commit ba7beb676d55b73334bd4a85623e56c713a83773 +Subproject commit 17e13a3a5078e76483f7c30a3b513507f0c9ebd6 diff --git a/rocket-chip b/rocket-chip index 7e75d63..47d63d6 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit 7e75d63ba6b4c1b50aaaf920e1c693ef6acf51d7 +Subproject commit 47d63d6baa840da26d9091a29294380cf399f4ad diff --git a/sifive-blocks b/sifive-blocks index 9052a07..3dee152 160000 --- a/sifive-blocks +++ b/sifive-blocks @@ -1 +1 @@ -Subproject commit 9052a079d404ebbfda5f01765b909c20503504ad +Subproject commit 3dee15277598e45d7ac9d435f0365989c6d00f7e diff --git a/src/main/scala/unleashed/u500vc707devkit/Config.scala b/src/main/scala/unleashed/u500vc707devkit/Config.scala index 4598f2f..4aa7362 100644 --- a/src/main/scala/unleashed/u500vc707devkit/Config.scala +++ b/src/main/scala/unleashed/u500vc707devkit/Config.scala @@ -26,11 +26,11 @@ class FreedomUVC707Config extends Config( // Freedom U500 VC707 Dev Kit Peripherals class U500VC707DevKitPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List( - UARTParams(address = BigInt(0x54000000L))) + UARTParams(address = BigInt(0x64000000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x54001000L))) + SPIParams(rAddress = BigInt(0x64001000L))) case PeripheryGPIOKey => List( - GPIOParams(address = BigInt(0x54002000L), width = 4)) + GPIOParams(address = BigInt(0x64002000L), width = 4)) case PeripheryMaskROMKey => List( MaskROMParams(address = 0x10000, name = "BootROM")) }) @@ -40,7 +40,7 @@ class U500VC707DevKitConfig extends Config( new WithNExtTopInterrupts(0) ++ new U500VC707DevKitPeripherals ++ new FreedomUVC707Config().alter((site,here,up) => { - case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff))) + case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128) case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB case DTSTimebase => BigInt(1000000) diff --git a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala index 9ac7667..2075116 100644 --- a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala +++ b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala @@ -30,7 +30,8 @@ object PinGen { class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707Shell with HasPCIe - with HasDDR3 { + with HasDDR3 + with HasDebugJTAG { //----------------------------------------------------------------------- // DUT