riscv/freedom
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freedom: bump submodules to their respective masters

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This commit is contained in:
Wesley W. Terpstra
2017-11-02 14:43:04 -07:00
parent 22ee433699
commit 4eaac79ec2
7 changed files with 40 additions and 19 deletions
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5
src/main/scala/unleashed/u500vc707devkit/Config.scala
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@@ -13,6 +13,8 @@ import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams}
// Default FreedomUVC707Config
class FreedomUVC707Config extends Config(
new WithJtagDTM ++
@@ -40,7 +42,8 @@ class U500VC707DevKitConfig extends Config(
new U500VC707DevKitPeripherals ++
new FreedomUVC707Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
case PeripheryBusParams => up(PeripheryBusParams, site).copy(frequency = 50000000) // 50 MHz hperiphery
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case JtagDTMKey => new JtagDTMConfig (

9
src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala
View File

@@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.shell.xilinx.vc707shell.{VC707Shell}
import sifive.fpgashells.shell.xilinx.vc707shell._
import sifive.fpgashells.ip.xilinx.{IOBUF}
//-------------------------------------------------------------------------
@@ -27,7 +27,10 @@ object PinGen {
// U500VC707DevKitFPGAChip
//-------------------------------------------------------------------------
class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707Shell {
class U500VC707DevKitFPGAChip(implicit override val p: Parameters)
extends VC707Shell
with HasPCIe
with HasDDR3 {
//-----------------------------------------------------------------------
// DUT
@@ -55,7 +58,7 @@ class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707
val gpioParams = p(PeripheryGPIOKey)
val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
gpio_pins.fromPort(dut.gpio(0))
GPIOPinsFromPort(gpio_pins, dut.gpio(0))
gpio_pins.pins.foreach { _.i.ival := Bool(false) }
gpio_pins.pins.zipWithIndex.foreach {